JPS6387934U - - Google Patents

Info

Publication number
JPS6387934U
JPS6387934U JP1986182976U JP18297686U JPS6387934U JP S6387934 U JPS6387934 U JP S6387934U JP 1986182976 U JP1986182976 U JP 1986182976U JP 18297686 U JP18297686 U JP 18297686U JP S6387934 U JPS6387934 U JP S6387934U
Authority
JP
Japan
Prior art keywords
pattern
idle
reception
flop
flip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1986182976U
Other languages
Japanese (ja)
Other versions
JPH0526851Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1986182976U priority Critical patent/JPH0526851Y2/ja
Publication of JPS6387934U publication Critical patent/JPS6387934U/ja
Application granted granted Critical
Publication of JPH0526851Y2 publication Critical patent/JPH0526851Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図及び第2図は、各々この考案の一実施例
によるデータ伝送装置の送信部及び受信部を示す
ブロツク図、第3図及び第4図は、各々同データ
伝送装置の動作を説明するためのタイミングチヤ
ートである。 1:アイドル符号発生回路、2:オン符号発生
回路、3:セレクタ回路、4:アイドル符号検出
回路、5:オン符号検出回路、6:監視回路、7
:クランプ回路、8:アンドゲート、9:フリツ
プフロツプ。
1 and 2 are block diagrams showing a transmitter and a receiver, respectively, of a data transmission device according to an embodiment of the invention, and FIGS. 3 and 4, respectively, explain the operation of the data transmission device. This is a timing chart for. 1: Idle code generation circuit, 2: ON code generation circuit, 3: Selector circuit, 4: Idle code detection circuit, 5: ON code detection circuit, 6: Monitoring circuit, 7
: Clamp circuit, 8: AND gate, 9: Flip-flop.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 送信側から送出される送信要求信号がオフして
いる時には、アイドルパターンを発生し、前記送
信要求信号がオフからオンに変化した時には所定
長のオンパターンを発生すると共に、このオンパ
ターンにより受信検出信号を前記送信側へ送出し
てその後、前起送信側から送出されるデータを受
信し、前記アイドルパターンにより、前記受信検
出信号をオフするデータ伝送装置において、前記
オンパターンを検出するオン符号検出回路と、前
記アイドルパターンを検出するアイドル符号検出
回路と、前記オン符号検出回路が前記オンパター
ンを検出した時にセツトされて前記受信検出信号
をオンする一方、前記アイドル符号検出回路が前
記アイドルパターンを検出した時にリセツトされ
て前記受信検出信号をオフするフリツプフロツプ
と、前記アイドル符号検出回路により、前記アイ
ドルパターンが検出されなくなつた後、一定時間
内に前記オン符号検出回路が前記オンパターンを
検出しないときは前記フリツプフロツプをセツト
し、又、前記データが受信途中でダウンした後、
復旧したときは、前記フリツプフロツプをセツト
する監視回路とを具備することを特徴とするデー
タ伝送装置。
When the transmission request signal sent from the transmitting side is off, an idle pattern is generated, and when the transmission request signal changes from off to on, an on pattern of a predetermined length is generated, and reception is detected by this on pattern. On-sign detection for detecting the on-pattern in a data transmission device that transmits a signal to the transmitting side, then receives data sent from the preceding transmitting side, and turns off the reception detection signal based on the idle pattern. an idle code detection circuit for detecting the idle pattern, and an on-sign detection circuit that is set when detecting the on-pattern to turn on the reception detection signal; A flip-flop that is reset to turn off the reception detection signal when detected, and the idle code detection circuit, after the idle pattern is no longer detected, the on-sign detection circuit does not detect the on-pattern within a certain period of time. When the flip-flop is set, and after the data goes down during reception,
A data transmission device comprising: a monitoring circuit that sets the flip-flop when the flip-flop is restored.
JP1986182976U 1986-11-28 1986-11-28 Expired - Lifetime JPH0526851Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1986182976U JPH0526851Y2 (en) 1986-11-28 1986-11-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1986182976U JPH0526851Y2 (en) 1986-11-28 1986-11-28

Publications (2)

Publication Number Publication Date
JPS6387934U true JPS6387934U (en) 1988-06-08
JPH0526851Y2 JPH0526851Y2 (en) 1993-07-07

Family

ID=31129278

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1986182976U Expired - Lifetime JPH0526851Y2 (en) 1986-11-28 1986-11-28

Country Status (1)

Country Link
JP (1) JPH0526851Y2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63313940A (en) * 1987-06-17 1988-12-22 Hitachi Ltd Communication control device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56129452A (en) * 1980-03-15 1981-10-09 Keisatsuchiyou Chokan Synchronous control system
JPS56172048U (en) * 1981-05-22 1981-12-18
JPS57104342A (en) * 1980-12-20 1982-06-29 Fujitsu Ltd Frame synchronizing system
JPS57118453A (en) * 1981-01-14 1982-07-23 Matsushita Electric Ind Co Ltd Transmitting and receiving system of timing detection signal
JPS57191155U (en) * 1981-05-29 1982-12-03

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56129452A (en) * 1980-03-15 1981-10-09 Keisatsuchiyou Chokan Synchronous control system
JPS57104342A (en) * 1980-12-20 1982-06-29 Fujitsu Ltd Frame synchronizing system
JPS57118453A (en) * 1981-01-14 1982-07-23 Matsushita Electric Ind Co Ltd Transmitting and receiving system of timing detection signal
JPS56172048U (en) * 1981-05-22 1981-12-18
JPS57191155U (en) * 1981-05-29 1982-12-03

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63313940A (en) * 1987-06-17 1988-12-22 Hitachi Ltd Communication control device

Also Published As

Publication number Publication date
JPH0526851Y2 (en) 1993-07-07

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