JPH0186345U

JPH0186345U -

Info

Publication number: JPH0186345U
Application number: JP17998887U
Authority: JP
Priority date: 1987-11-25
Filing date: 1987-11-25
Publication date: 1989-06-07

Description

[Brief explanation of drawings]

第１図は本考案の一実施例の受信部のブロツク
回路図、第２図は符号変換装置使用システム図、
第３図は符号変換過程のタイミング図、第４図は
従来の一例の受信部のブロツク回路図である。１……調歩式非同期信号、２……同期化符号、
３……非同期符号、５……１キヤラクタシフト終
了信号、６……シフトパルス、７……カウンタリ
セツトパルス、８，１０，１２……パラレル出力
、９……正常キヤラクタ計数回路出力信号、１１
……シフトパルス、１３……送信部、１４……受
信部、１５……スタート・ストツプ検出回路、１
６……シフトレジスタ、１７……制御回路、１８
……シフトレジスタ、１９……調歩同期検出回路
、２０……正常キヤラクタ計数回路、２１……削
除ビツト確認信号、２２……スタート・ストツプ
検出信号、２３……削除ビツト検出信号。 FIG. 1 is a block circuit diagram of a receiving section according to an embodiment of the present invention, and FIG. 2 is a system diagram using a code conversion device.
FIG. 3 is a timing diagram of the code conversion process, and FIG. 4 is a block circuit diagram of a conventional receiving section. 1... Start-stop asynchronous signal, 2... Synchronization code,
3...Asynchronous code, 5...1 character shift end signal, 6...Shift pulse, 7...Counter reset pulse, 8, 10, 12...Parallel output, 9...Normal character counting circuit output signal, 11
...shift pulse, 13...transmitter, 14...receiver, 15...start/stop detection circuit, 1
6...Shift register, 17...Control circuit, 18
...Shift register, 19...Start-stop synchronization detection circuit, 20...Normal character counting circuit, 21...Deletion bit confirmation signal, 22...Start/stop detection signal, 23...Deletion bit detection signal.

Claims

[Scope of utility model registration request]

A transmitter that deletes stop bits when the code speed of the asynchronous code is faster than the code speed of the synchronous code, performs synchronous encoding, and transmits the code; and a transmitter that receives the synchronous code, detects the deleted stop bits, and regenerates and adds stop bits thereto. and a receiving section that performs asynchronous encoding, and this receiving section includes an asynchronous detection circuit,
In the asynchronous/synchronous code conversion device having a first shift register, a second shift register, and a control circuit, one shift register of the receiving section is replaced with three shift registers.
A normal character counting circuit is connected to this first shift register and detects that a normal character code with no deletion bits is received consecutively for a specified number of characters or more, and also connected to the first shift register. A start/stop detection circuit is added to detect the sign of the stop bit position of the character following the character detected by the character.
Asynchronous and synchronous, characterized in that the control circuit is provided with a determination means for determining whether a deletion bit should be inserted or whether the sign should be inverted as an error based on the output signals from the normal character counting circuit and the start/stop detection circuit. Code conversion circuit.