JPS62127146U - - Google Patents
Info
- Publication number
- JPS62127146U JPS62127146U JP1398286U JP1398286U JPS62127146U JP S62127146 U JPS62127146 U JP S62127146U JP 1398286 U JP1398286 U JP 1398286U JP 1398286 U JP1398286 U JP 1398286U JP S62127146 U JPS62127146 U JP S62127146U
- Authority
- JP
- Japan
- Prior art keywords
- data
- circuit
- signal
- clock
- receiving
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims 2
- 230000005540 biological transmission Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
Landscapes
- Time-Division Multiplex Systems (AREA)
- Dc Digital Transmission (AREA)
- Small-Scale Networks (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Description
第１図はこの考案の一実施例に係るシリアルデ
ータ伝送装置のブロツク図、第２図はその各部の
信号状態を示すタイムチヤートである。
１……シリアルデータ伝送装置、７……送信機
、９……受信機、１１……データ線、１９……送
信用時計、２１……Ｐ／Ｓ変換回路、２３……デ
ータ加追回路、３３……受信用回路、３５……パ
ルス信号発生回路、３７……Ｓ／Ｐ変換回路、４
１……追加データ消去回路。
FIG. 1 is a block diagram of a serial data transmission device according to an embodiment of the invention, and FIG. 2 is a time chart showing signal states of each part thereof. 1... Serial data transmission device, 7... Transmitter, 9... Receiver, 11... Data line, 19... Transmission clock, 21... P/S conversion circuit, 23... Data addition circuit, 33... Receiving circuit, 35... Pulse signal generation circuit, 37... S/P conversion circuit, 4
1...Additional data erasing circuit.
Claims (1)
用時計と、２値で表現される複数ビツトの送信デ
ータの途中に先に送信されるビツトデータと異種
のデータを追加するデータ追加回路と、この回路
で追加された複数ビツトのデータを前記時計信号
に同期してＮＲＺ信号で送信するデータ送信回路
と、を備え、受信機に、所定周波の時計信号を出
力する受信用時計と、この時計信号に同期して前
記送信データを受信するデータ受信回路と、少な
くとも前記データ追加回路で追加されたデータと
このデータより先に受信されたデータとの境界で
信号レベルの変化を検出するレベル変化検出回路
と、この回路の検出信号に基いて前記受信用時計
をリセツトする受信用時計リセツト回路と、受信
データから前記追加のデータを消去する追加デー
タ消去回路と、を備えて構成されるシリアルデー
タ伝送装置。 A transmitting clock that outputs a clock signal of a predetermined frequency to a transmitter, a data addition circuit that adds data different from the bit data transmitted earlier to the middle of multiple bits of transmitted data expressed in binary values; a data transmitting circuit that transmits multiple bits of data added by this circuit as an NRZ signal in synchronization with the clock signal; a receiving clock that outputs a clock signal of a predetermined frequency to a receiver; a data receiving circuit that receives the transmitted data in synchronization with a signal, and a level change detection that detects a change in signal level at least at the boundary between data added by the data adding circuit and data received earlier than this data. A receiving clock reset circuit that resets the receiving clock based on a detection signal of this circuit, and an additional data erasing circuit that erases the additional data from received data. Device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1398286U JPS62127146U (en) | 1986-02-04 | 1986-02-04 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1398286U JPS62127146U (en) | 1986-02-04 | 1986-02-04 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62127146U true JPS62127146U (en) | 1987-08-12 |
Family
ID=30803550
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1398286U Pending JPS62127146U (en) | 1986-02-04 | 1986-02-04 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62127146U (en) |
-
1986
- 1986-02-04 JP JP1398286U patent/JPS62127146U/ja active Pending
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