JPH03113554U

JPH03113554U -

Info

Publication number: JPH03113554U
Application number: JP2279290U
Authority: JP
Priority date: 1990-03-07
Filing date: 1990-03-07
Publication date: 1991-11-20

Description

[Brief explanation of drawings]

第１図はこの考案の１実施例を示す構成ブロツ
ク図、第２図は従来の回路の構成ブロツク図、第
３図、第４図、第５図、第６図、第７図は信号受
信器の入出力波形を示す図である。図において、１は入力クロツク、２は信号送信
器、３は伝送線路、４は信号受信器、５は出力ク
ロツク、６は受信器入力波形、７は出力波形、８
は「スレツシヨルド」を示す電圧の位置、１０は
「ハイ」信号レベル、１１は「ロー」信号レベル
、１２は受信器入力波形、１３は出力波形、１４
は受信器入力波形、１５は出力波形、１６は信号
受信器、１７は電圧検出器、１８は平均値検出器
、１９はスレツシヨルド設定器、２０は初期値設
定器、２１は出力波形、２２は「スレツシヨルド
」を示す電圧の位置、２３は出力波形、２４は「
スレツシヨルド」を示す電圧の位置を示す。なお
、図中同一あるいは相当部分には同一符号を付し
て示してある。 Figure 1 is a block diagram showing an embodiment of this invention, Figure 2 is a block diagram of a conventional circuit, and Figures 3, 4, 5, 6, and 7 are for signal reception. FIG. 3 is a diagram showing input and output waveforms of the device. In the figure, 1 is the input clock, 2 is the signal transmitter, 3 is the transmission line, 4 is the signal receiver, 5 is the output clock, 6 is the receiver input waveform, 7 is the output waveform, 8
is the voltage position indicating the "threshold", 10 is the "high" signal level, 11 is the "low" signal level, 12 is the receiver input waveform, 13 is the output waveform, 14
is the receiver input waveform, 15 is the output waveform, 16 is the signal receiver, 17 is the voltage detector, 18 is the average value detector, 19 is the threshold setter, 20 is the initial value setter, 21 is the output waveform, and 22 is the The position of the voltage indicating the "threshold", 23 is the output waveform, and 24 is the "
Indicates the position of the voltage that indicates the “threshold”. It should be noted that the same or corresponding parts in the figures are indicated by the same reference numerals.

Claims

[Scope of utility model registration request]

A clock to be transmitted, a signal transmitter that transmits the clock to the transmission line, a signal receiver that receives the clock transmitted to the transmission line and transmitted on the transmission line, and a clock that is input to the signal receiver. A voltage detector that detects voltage, an average value detector that detects the average value of the detected voltage, a threshold setter that sets the average value as a "threshold," and an initial value setter for the threshold setter. , an interface circuit characterized in that clock transmission of the signal receiver is performed according to the set "threshold".