JPS62121858U - - Google Patents
Info
- Publication number
- JPS62121858U JPS62121858U JP851286U JP851286U JPS62121858U JP S62121858 U JPS62121858 U JP S62121858U JP 851286 U JP851286 U JP 851286U JP 851286 U JP851286 U JP 851286U JP S62121858 U JPS62121858 U JP S62121858U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- receiver
- threshold
- level
- integrating circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005540 biological transmission Effects 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Dc Digital Transmission (AREA)
- Manipulation Of Pulses (AREA)
Description
第１図は本考案の一実施例を示す構成図、第２
図は説明のための波形図、第３図は従来の伝送装
置の構成図、第４図は従来の伝送状態を説明する
ための波形図である。
１……送信器、２……受信器、３……伝送路、
７……整流器、８……積分回路、９……スレツシ
ホールド制御回路。
Fig. 1 is a configuration diagram showing one embodiment of the present invention;
The figure is a waveform diagram for explanation, FIG. 3 is a configuration diagram of a conventional transmission device, and FIG. 4 is a waveform diagram for explaining a conventional transmission state. 1... Transmitter, 2... Receiver, 3... Transmission line,
7... Rectifier, 8... Integrating circuit, 9... Threshold control circuit.
Claims (1)
信器にて受信して整形復調するものに於て、前記
受信器に入力される信号を導入して整流する整流
器と、この整流器にて整流された信号を積分回路
を通して導入し、積分回路よりの信号あり時には
ローレベルのスレツシホールド信号として前記受
信器に出力し、且つ積分回路よりの信号が一定レ
ベル以下時にはハイレベルのスレツシホールド信
号として受信器に出力するスレツシホールド制御
回路とを備え、スレツシホールド信号に基いて受
信器のスレツシホールドレベルを制御するよう構
成したことを特徴とする受信装置。 A receiver receives and shapes and demodulates a signal sent from a transmitter via a transmission path, and includes a rectifier that introduces and rectifies the signal input to the receiver, and a rectifier that rectifies the signal that is input to the receiver. The resulting signal is introduced through the integrating circuit, and when there is a signal from the integrating circuit, it is output as a low-level threshold signal to the receiver, and when the signal from the integrating circuit is below a certain level, it is output as a high-level threshold signal. 1. A receiver comprising: a threshold control circuit that outputs a threshold signal to a receiver, and is configured to control a threshold level of the receiver based on a threshold signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP851286U JPS62121858U (en) | 1986-01-24 | 1986-01-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP851286U JPS62121858U (en) | 1986-01-24 | 1986-01-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62121858U true JPS62121858U (en) | 1987-08-03 |
Family
ID=30792955
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP851286U Pending JPS62121858U (en) | 1986-01-24 | 1986-01-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62121858U (en) |
-
1986
- 1986-01-24 JP JP851286U patent/JPS62121858U/ja active Pending
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