JPS6251839U - - Google Patents

Info

Publication number
JPS6251839U
JPS6251839U JP14301085U JP14301085U JPS6251839U JP S6251839 U JPS6251839 U JP S6251839U JP 14301085 U JP14301085 U JP 14301085U JP 14301085 U JP14301085 U JP 14301085U JP S6251839 U JPS6251839 U JP S6251839U
Authority
JP
Japan
Prior art keywords
signal
pulse train
train signal
monostable multivibrator
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14301085U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP14301085U priority Critical patent/JPS6251839U/ja
Publication of JPS6251839U publication Critical patent/JPS6251839U/ja
Pending legal-status Critical Current

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  • Dc Digital Transmission (AREA)
  • Selective Calling Equipment (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例における受信回路の
ブロツク図、第2図は第1図の具体的回路図、第
3図及び第4図は第1図のタイムチヤート、第5
図は従来の受信回路のブロツク図、第6図、第7
図及び第8図は夫々第5図のタイムチヤートであ
る。 1…送信部、2…受信部、21…遅延回路、2
2…第1モノマルチ、23…Dフリツプフロツプ
、24…入力処理部、25…第2モノマルチ。
FIG. 1 is a block diagram of a receiving circuit in an embodiment of the present invention, FIG. 2 is a specific circuit diagram of FIG. 1, FIGS. 3 and 4 are time charts of FIG. 1, and FIG.
The figures are block diagrams of conventional receiving circuits, Figures 6 and 7.
8 and 8 are time charts of FIG. 5, respectively. DESCRIPTION OF SYMBOLS 1... Transmission part, 2... Receiving part, 21... Delay circuit, 2
2...First monomulti, 23...D flip-flop, 24...Input processing section, 25...Second monomulti.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 送信部より送信され、2値信号がパルス間隔の
長短に変換されたパルス列信号を受信するリモー
トコントロール装置の受信回路であつて、受信し
た前記パルス信号を少許遅延せしめる遅延回路と
、この遅延回路出力によりトリガされる再トリガ
型の第1安定マルチバイブレータと、前記パルス
列信号のパルスのタイミングで前記第1の単安定
マルチバイブレータ出力レベルを判別し、元の2
値信号に復号する信号処理部とを備える受信回路
において前記受信したパルス列信号のパヌス間隔
のうち一番短かいパルス間隔よりも若干短い準安
定期間を有し、前記パルス列信号によりトリガさ
れる第2の単安定マルチバイブレータを設け、こ
の第2の単安定マルチバイブレータ出力のタイミ
ングで前記第1の単安定マルチバイブレータ出力
レベルを判別することを特徴とするリモートコン
トロール装置の受信回路。
A receiving circuit of a remote control device that receives a pulse train signal transmitted from a transmitter and in which a binary signal is converted into a long or short pulse interval, the delay circuit delaying the received pulse signal by a certain amount of time, and the output of this delay circuit. The retrigger type first stable multivibrator triggered by
and a signal processing unit that decodes the received pulse train signal into a value signal, the second pulse train signal has a metastable period slightly shorter than the shortest pulse interval among the panus intervals of the received pulse train signal, and is triggered by the pulse train signal. A receiving circuit for a remote control device, characterized in that a monostable multivibrator is provided, and the output level of the first monostable multivibrator is determined at the timing of the output of the second monostable multivibrator.
JP14301085U 1985-09-19 1985-09-19 Pending JPS6251839U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14301085U JPS6251839U (en) 1985-09-19 1985-09-19

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14301085U JPS6251839U (en) 1985-09-19 1985-09-19

Publications (1)

Publication Number Publication Date
JPS6251839U true JPS6251839U (en) 1987-03-31

Family

ID=31052289

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14301085U Pending JPS6251839U (en) 1985-09-19 1985-09-19

Country Status (1)

Country Link
JP (1) JPS6251839U (en)

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