JPS6451322U - - Google Patents

Info

Publication number
JPS6451322U
JPS6451322U JP14482687U JP14482687U JPS6451322U JP S6451322 U JPS6451322 U JP S6451322U JP 14482687 U JP14482687 U JP 14482687U JP 14482687 U JP14482687 U JP 14482687U JP S6451322 U JPS6451322 U JP S6451322U
Authority
JP
Japan
Prior art keywords
monostable multivibrator
switch signal
input
switch
latching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14482687U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP14482687U priority Critical patent/JPS6451322U/ja
Publication of JPS6451322U publication Critical patent/JPS6451322U/ja
Pending legal-status Critical Current

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  • Manipulation Of Pulses (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本考案の一実施例によるチヤタリン
グ防止回路の構成を示すブロツク図、第2図は、
第1図のチヤタリング防止回路の動作を説明する
ためのタイミング図、第3図は、従来のチヤタリ
ング防止回路の構成を示すブロツク図、および第
4図は、従来の別のチヤタリング防止回路の構成
を示すブロツク図である。 図面において、10……スイツチ、12……抵
抗、14……コンデンサ、16……単安定マルチ
バイブレータ(モノマルチ)、22……D型フリ
ツプフロツプ。
FIG. 1 is a block diagram showing the configuration of a chattering prevention circuit according to an embodiment of the present invention, and FIG.
FIG. 1 is a timing diagram for explaining the operation of the chattering prevention circuit, FIG. 3 is a block diagram showing the configuration of a conventional chattering prevention circuit, and FIG. 4 is a diagram showing the configuration of another conventional chattering prevention circuit. FIG. In the drawings, 10...switch, 12... resistor, 14... capacitor, 16... monostable multivibrator (mono multi), 22... D type flip-flop.

Claims (1)

【実用新案登録請求の範囲】 動作時にチヤタリングを起こすスイツチより得
られる二値レベルのスイツチ信号を入力する単安
定マルチバイブレータと、 前記単安定マルチバイブレータの出力信号と前
記スイツチ信号とを入力し、前記単安定マルチバ
イブレータより出力されたパルスの終端で前記ス
イツチ信号のレベルをラツチするラツチ手段と、
を具備することを特徴とするチヤタリング防止回
路。
[Claims for Utility Model Registration] A monostable multivibrator into which a binary level switch signal obtained from a switch that causes chattering during operation is input; an output signal of the monostable multivibrator and the switch signal are input; latching means for latching the level of the switch signal at the end of the pulse output from the monostable multivibrator;
A chattering prevention circuit characterized by comprising:
JP14482687U 1987-09-22 1987-09-22 Pending JPS6451322U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14482687U JPS6451322U (en) 1987-09-22 1987-09-22

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14482687U JPS6451322U (en) 1987-09-22 1987-09-22

Publications (1)

Publication Number Publication Date
JPS6451322U true JPS6451322U (en) 1989-03-30

Family

ID=31412873

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14482687U Pending JPS6451322U (en) 1987-09-22 1987-09-22

Country Status (1)

Country Link
JP (1) JPS6451322U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7642086B2 (en) 2005-08-09 2010-01-05 Canon Kabushiki Kaisha Labeled probe bound object, method for producing the same and method for using the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7642086B2 (en) 2005-08-09 2010-01-05 Canon Kabushiki Kaisha Labeled probe bound object, method for producing the same and method for using the same

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