JPS63106220U - - Google Patents
Info
- Publication number
- JPS63106220U JPS63106220U JP1986201543U JP20154386U JPS63106220U JP S63106220 U JPS63106220 U JP S63106220U JP 1986201543 U JP1986201543 U JP 1986201543U JP 20154386 U JP20154386 U JP 20154386U JP S63106220 U JPS63106220 U JP S63106220U
- Authority
- JP
- Japan
- Prior art keywords
- flip
- flop
- circuit
- delay line
- pulse width
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001934 delay Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Pulse Circuits (AREA)
Description
第１図はこの考案の高速パルス波用遅延回路の
一実施例のブロツク図、第２図は従来技術におけ
る遅延回路の一例のブロツク図、第３図は上記実
施例の動作を設明するためのブロツク図である。
１２……デイレーライン、１３……フリツプフ
ロツプ回路、１４……パルス幅設定回路。
Fig. 1 is a block diagram of an embodiment of the delay circuit for high-speed pulse waves of this invention, Fig. 2 is a block diagram of an example of a delay circuit in the prior art, and Fig. 3 is for explaining the operation of the above embodiment. FIG. 12...Delay line, 13...Flip-flop circuit, 14...Pulse width setting circuit.
Claims (1)
レーラインと； このデイレーラインの出力によりセツトされる
フリツプフロツプ回路と； このフリツプフロツプがセツトされてから上記
入力パルス信号のパルス幅に等しい時間後にリセ
ツト信号を出力してフリツプフロツプをリセツト
するパルス幅設定回路と； を具備したことを特徴とする高速パルス波用遅延
回路。[Claims for Utility Model Registration] A delay line that delays an input pulse signal by a predetermined time; A flip-flop circuit that is set by the output of this delay line; A pulse width of the input pulse signal after this flip-flop is set; 1. A delay circuit for high-speed pulse waves, comprising: a pulse width setting circuit that resets a flip-flop by outputting a reset signal after a time equal to .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986201543U JPS63106220U (en) | 1986-12-26 | 1986-12-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986201543U JPS63106220U (en) | 1986-12-26 | 1986-12-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63106220U true JPS63106220U (en) | 1988-07-09 |
Family
ID=31165097
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986201543U Pending JPS63106220U (en) | 1986-12-26 | 1986-12-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63106220U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4873054A (en) * | 1971-12-24 | 1973-10-02 | ||
| JPS50119557A (en) * | 1974-03-02 | 1975-09-19 |
-
1986
- 1986-12-26 JP JP1986201543U patent/JPS63106220U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4873054A (en) * | 1971-12-24 | 1973-10-02 | ||
| JPS50119557A (en) * | 1974-03-02 | 1975-09-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS63106220U (en) | ||
| JPS61176825U (en) | ||
| JPS61131130U (en) | ||
| JPH0163224U (en) | ||
| JPS6416740U (en) | ||
| JPS62198724U (en) | ||
| JPH0412715U (en) | ||
| JPS643329U (en) | ||
| JPS61140638U (en) | ||
| JPS60119138U (en) | Pulse generation circuit | |
| JPH0357630U (en) | ||
| JPH0310639U (en) | ||
| JPS61128841U (en) | ||
| JPS6333254U (en) | ||
| JPS61134125U (en) | ||
| JPH01162392U (en) | ||
| JPS6289880U (en) | ||
| JPH0226200U (en) | ||
| JPH0257630U (en) | ||
| JPS58522U (en) | Pulse width shaping circuit | |
| JPS62203521U (en) | ||
| JPS645532U (en) | ||
| JPS633629U (en) | ||
| JPH02148474U (en) | ||
| JPH0381574U (en) |