JPS62181044U - - Google Patents
Info
- Publication number
- JPS62181044U JPS62181044U JP6944186U JP6944186U JPS62181044U JP S62181044 U JPS62181044 U JP S62181044U JP 6944186 U JP6944186 U JP 6944186U JP 6944186 U JP6944186 U JP 6944186U JP S62181044 U JPS62181044 U JP S62181044U
- Authority
- JP
- Japan
- Prior art keywords
- output signal
- flip
- flop circuit
- circuit
- timer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Electronic Switches (AREA)
- Measurement Of Predetermined Time Intervals (AREA)
Description
第１図はこの考案のパルススイツチのカウント
回路の一実施例のブロツク図、第２図は同上パル
ススイツチのカウント回路の動作の流れを示すフ
ローチヤート、第３図は同上パルススイツチのカ
ウント回路の動作を説明するためのタイムチヤー
ト、第４図は従来のパルススイツチのカウント回
路のブロツク図である。
１……マイクロコンピユータ、２……フリツプ
フロツプ回路、３……パルススイツチ。
Fig. 1 is a block diagram of one embodiment of the counting circuit of the pulse switch of this invention, Fig. 2 is a flowchart showing the operation flow of the counting circuit of the pulse switch mentioned above, and Fig. 3 is the counting circuit of the pulse switch mentioned above. FIG. 4 is a time chart for explaining the operation, and is a block diagram of a conventional pulse switch counting circuit. 1...Microcomputer, 2...Flip-flop circuit, 3...Pulse switch.
Claims (1)
入力すると、セツトされて出力信号を発するフリ
ツプフロツプ回路と、このフリツプフロツプ回路
の出力信号が発生するごとに、タイマがセツトさ
れ、上記出力信号をカウントし、かつ上記タイマ
により定められる所定期間内に上記出力信号が入
力されないときには、上記フリツプフロツプ回路
をリセツトするマイクロコンピユータまたはハー
ドロジツク回路とよりなるパルススイツチのカウ
ント回路。 When a pulse generated every time the pulse switch is operated, a flip-flop circuit is set and outputs an output signal, and each time an output signal of this flip-flop circuit is generated, a timer is set to count the output signal and output the output signal. A pulse switch counting circuit comprising a microcomputer or hard logic circuit that resets the flip-flop circuit when the output signal is not input within a predetermined period determined by a timer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6944186U JPS62181044U (en) | 1986-05-09 | 1986-05-09 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6944186U JPS62181044U (en) | 1986-05-09 | 1986-05-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62181044U true JPS62181044U (en) | 1987-11-17 |
Family
ID=30910177
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6944186U Pending JPS62181044U (en) | 1986-05-09 | 1986-05-09 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62181044U (en) |
-
1986
- 1986-05-09 JP JP6944186U patent/JPS62181044U/ja active Pending