JPH01155544U - - Google Patents

Info

Publication number
JPH01155544U
JPH01155544U JP5172688U JP5172688U JPH01155544U JP H01155544 U JPH01155544 U JP H01155544U JP 5172688 U JP5172688 U JP 5172688U JP 5172688 U JP5172688 U JP 5172688U JP H01155544 U JPH01155544 U JP H01155544U
Authority
JP
Japan
Prior art keywords
timer
cpu
counter
holding means
data holding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5172688U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP5172688U priority Critical patent/JPH01155544U/ja
Publication of JPH01155544U publication Critical patent/JPH01155544U/ja
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

図面はそれぞれタイマ装置のブロツク図を示し
、第1図は本考案の1実施例、第2図は従来例で
ある。 1……タイマカウンタ、4……フリツプフロツ
プ、5……タイマ出力切替回路。
The drawings each show a block diagram of a timer device, with FIG. 1 showing one embodiment of the present invention and FIG. 2 showing a conventional example. 1...Timer counter, 4...Flip-flop, 5...Timer output switching circuit.

Claims (1)

【実用新案登録請求の範囲】 CPUで処理されるプログラムの暴走を監視す
るタイマ装置において、 クロツクパルスを計数し前記CPUからのソフ
トリセツト信号によりクリアされるタイマカウン
タと、該カウンタのタイムアウト信号によりセツ
トされシステムリセツト信号を出力するデータ保
持手段と、前記CPUからの特定データの書き込
みを判断して前記データ保持手段をクリアするタ
イマ出力切替回路とを備えてなるタイマ装置。
[Claim for Utility Model Registration] A timer device for monitoring runaway of a program processed by a CPU includes a timer counter that counts clock pulses and is cleared by a soft reset signal from the CPU, and a timer counter that is reset by a timeout signal of the counter. A timer device comprising a data holding means for outputting a system reset signal, and a timer output switching circuit for determining writing of specific data from the CPU and clearing the data holding means.
JP5172688U 1988-04-18 1988-04-18 Pending JPH01155544U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5172688U JPH01155544U (en) 1988-04-18 1988-04-18

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5172688U JPH01155544U (en) 1988-04-18 1988-04-18

Publications (1)

Publication Number Publication Date
JPH01155544U true JPH01155544U (en) 1989-10-25

Family

ID=31277742

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5172688U Pending JPH01155544U (en) 1988-04-18 1988-04-18

Country Status (1)

Country Link
JP (1) JPH01155544U (en)

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