JPH01110522U - - Google Patents

Info

Publication number
JPH01110522U
JPH01110522U JP626588U JP626588U JPH01110522U JP H01110522 U JPH01110522 U JP H01110522U JP 626588 U JP626588 U JP 626588U JP 626588 U JP626588 U JP 626588U JP H01110522 U JPH01110522 U JP H01110522U
Authority
JP
Japan
Prior art keywords
circuit
pulse
counter circuit
generates
changing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP626588U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP626588U priority Critical patent/JPH01110522U/ja
Publication of JPH01110522U publication Critical patent/JPH01110522U/ja
Pending legal-status Critical Current

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  • Pulse Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例の構成を示すブロツ
ク図、第2図aおよびbは第1図に示す本考案の
一実施例の部分の詳細を示す回路図、第3図aお
よびbは第1図に示す本考案の一実施例の動作を
示すタイミングチヤートおよび説明図、第4図は
従来技術によるパルス回路の一例を示す回路図、
第5図は第4図に示す従来の技術によるパルス回
路の一例の作動を示すタイミングチヤート。 1…カウンタ回路、2…組み合せ回路、11〜
13…組み合せ回路、14〜16…フリツプフロ
ツプ。
FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIGS. 2 a and b are circuit diagrams showing details of the part of the embodiment of the present invention shown in FIG. 1, and FIGS. 3 a and b 1 is a timing chart and an explanatory diagram showing the operation of an embodiment of the present invention shown in FIG. 1, and FIG. 4 is a circuit diagram showing an example of a pulse circuit according to the prior art.
FIG. 5 is a timing chart showing the operation of an example of the conventional pulse circuit shown in FIG. 4. 1...Counter circuit, 2...Combination circuit, 11~
13...Combination circuit, 14-16...Flip-flop.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] プログラム可能な論理素子で実現しカウントす
る順序を入れ変えることの可能なカウンタ回路と
、前記カウンタ回路の出力の連続した複数個のカ
ウント値の間パルスを発生させる組合せ回路とを
備えて成ることを特徴とするパルス回路。
A counter circuit realized by a programmable logic element and capable of changing the counting order, and a combination circuit that generates a pulse between a plurality of consecutive count values output from the counter circuit. Characteristic pulse circuit.
JP626588U 1988-01-20 1988-01-20 Pending JPH01110522U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP626588U JPH01110522U (en) 1988-01-20 1988-01-20

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP626588U JPH01110522U (en) 1988-01-20 1988-01-20

Publications (1)

Publication Number Publication Date
JPH01110522U true JPH01110522U (en) 1989-07-26

Family

ID=31210349

Family Applications (1)

Application Number Title Priority Date Filing Date
JP626588U Pending JPH01110522U (en) 1988-01-20 1988-01-20

Country Status (1)

Country Link
JP (1) JPH01110522U (en)

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