JPS61128840U - - Google Patents
Info
- Publication number
- JPS61128840U JPS61128840U JP1167185U JP1167185U JPS61128840U JP S61128840 U JPS61128840 U JP S61128840U JP 1167185 U JP1167185 U JP 1167185U JP 1167185 U JP1167185 U JP 1167185U JP S61128840 U JPS61128840 U JP S61128840U
- Authority
- JP
- Japan
- Prior art keywords
- code
- output
- dmi
- discriminator
- exclusive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005540 biological transmission Effects 0.000 claims 1
- 230000001934 delay Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Dc Digital Transmission (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Description
第１図は本考案の一実施例を示すブロツク図、
第２図は上記実施例の各部信号の一例を示すタイ
ムチヤート、第３図は従来のＤＭＩデコーダ回路
の一例を示すブロツク図、第４図は上記従来例の
各部信号を示すタイムチヤートである。
図において、１，４：識別器、２：遅延素子、
３：排他的論理和回路。
FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a time chart showing an example of various signals of the above embodiment, FIG. 3 is a block diagram showing an example of a conventional DMI decoder circuit, and FIG. 4 is a time chart showing various signals of the conventional example. In the figure, 1, 4: discriminator, 2: delay element,
3: Exclusive OR circuit.
Claims (1)
号伝送速度の1/2速度のクロツクで前記受信ＤＭ
Ｉ符号を識別する識別器と、該識別器の出力を前
記クロツクの１周期分遅延させる遅延素子と、該
遅延素子の出力と前記識別器の出力の排他的論理
和をとる排他的論理和回路とを備えて、該排他的
論理和回路の出力によつて前記受信ＤＭＩ符号を
原符号に復号することを特徴とするＤＭＩデコー
ダ回路。 The received DM is clocked at 1/2 speed of the DMI code transmission rate input in synchronization with the received DMI code.
a discriminator that identifies an I code; a delay element that delays the output of the discriminator by one cycle of the clock; and an exclusive OR circuit that takes an exclusive OR of the output of the delay element and the output of the discriminator. A DMI decoder circuit comprising: decoding the received DMI code into an original code using the output of the exclusive OR circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1167185U JPS61128840U (en) | 1985-01-30 | 1985-01-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1167185U JPS61128840U (en) | 1985-01-30 | 1985-01-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61128840U true JPS61128840U (en) | 1986-08-12 |
Family
ID=30494006
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1167185U Pending JPS61128840U (en) | 1985-01-30 | 1985-01-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61128840U (en) |
-
1985
- 1985-01-30 JP JP1167185U patent/JPS61128840U/ja active Pending