JPH0326191U - - Google Patents

Description

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an RGB circuit showing an embodiment of the present invention, FIG. 2 is a signal timing diagram for explaining the operation of the RGB circuit shown in FIG. 1, and FIG.
The figure is a block diagram of a conventional RGB circuit. 1...Oscillation circuit, 2...Clock delay circuit, 3
...Latch circuit, 4...Extraction circuit, 5...VS delay circuit.

Claims (1)

[Scope of utility model registration request] An oscillation circuit and an output signal of the oscillation circuit are input, and a first delay signal group of n pieces has a delay amount that is an even number multiple of the basic delay amount, and a second group of n pieces of delay signals that have a delay amount that is an odd number multiple of the basic delay amount. a clock delay circuit that outputs a vertical synchronization signal, a VS delay circuit that can delay the vertical synchronization signal and vary the amount of delay, a latch circuit that samples the one group of delayed signals based on the output signal of the VS delay circuit, and the latch circuit. When the output states of the n output signals differ by a delay amount of m and m+2 times, m+ of the other delayed signal group
and an extraction circuit that extracts a one-time delayed output.