JPS60177539U - Television receiver synchronization separation circuit - Google Patents
Television receiver synchronization separation circuitInfo
- Publication number
- JPS60177539U JPS60177539U JP6530784U JP6530784U JPS60177539U JP S60177539 U JPS60177539 U JP S60177539U JP 6530784 U JP6530784 U JP 6530784U JP 6530784 U JP6530784 U JP 6530784U JP S60177539 U JPS60177539 U JP S60177539U
- Authority
- JP
- Japan
- Prior art keywords
- separation circuit
- television receiver
- synchronization separation
- sync
- receiver synchronization
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Synchronizing For Television (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
図面は本考案の実施例を示すもので、第１図は本考案の
第１実施例を示す回路構成図、第２図は同実施例の動作
を説明するためのタイミングチャート、第３図は本考案
の第２実施例を示す回路構成図、第４図は本考案の第３
実施例における主要 一部分を示す回路構成図、第５
図は同実施例の動作を説明するためのタイミングチャー
ト、第６図は゛本考案の第４実施例を示す回路構成図で
ある。
１・・・同期分離回路、２・・・ＩＨ遅延回路、３・・
・アンド回路、１１・・・トランジスタ、２１・・・超
音波遅延線、２２・・・トランジスタ、２３・・・シフ
トレジスタ、２６・・・メモリ、２７・・・３１進カウ
ンタ。The drawings show an embodiment of the present invention. Fig. 1 is a circuit configuration diagram showing the first embodiment of the invention, Fig. 2 is a timing chart for explaining the operation of the embodiment, and Fig. 3 is a timing chart for explaining the operation of the embodiment. A circuit configuration diagram showing the second embodiment of the present invention, FIG. 4 is a circuit diagram showing the third embodiment of the present invention.
Circuit configuration diagram showing main parts in the embodiment, No. 5
The figure is a timing chart for explaining the operation of the same embodiment, and FIG. 6 is a circuit configuration diagram showing a fourth embodiment of the present invention. 1... Synchronization separation circuit, 2... IH delay circuit, 3...
・AND circuit, 11...Transistor, 21...Ultrasonic delay line, 22...Transistor, 23...Shift register, 26...Memory, 27...31-decimal counter.
Claims (1)
離回路と、この同期分離回路で分離された同期信号を１
水平期間遅らせる遅延素子と、この遅延素子の出力と上
記同期分離回路の出力信号との論理積を求める論理積素
子とを具備したことを特徴とするテレビジョン受像機の
同期分離回路。A sync separation circuit that separates sync signals included in a television video signal, and a sync signal separated by this sync separation circuit.
1. A synchronization separation circuit for a television receiver, comprising: a delay element for delaying a horizontal period; and an AND element for calculating the logical product of the output of the delay element and the output signal of the synchronization separation circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6530784U JPS60177539U (en) | 1984-05-02 | 1984-05-02 | Television receiver synchronization separation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6530784U JPS60177539U (en) | 1984-05-02 | 1984-05-02 | Television receiver synchronization separation circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60177539U true JPS60177539U (en) | 1985-11-26 |
Family
ID=30597189
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6530784U Pending JPS60177539U (en) | 1984-05-02 | 1984-05-02 | Television receiver synchronization separation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60177539U (en) |
-
1984
- 1984-05-02 JP JP6530784U patent/JPS60177539U/en active Pending
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