JPS6133546U - data transfer device - Google Patents

data transfer device

Info

Publication number
JPS6133546U
JPS6133546U JP11471884U JP11471884U JPS6133546U JP S6133546 U JPS6133546 U JP S6133546U JP 11471884 U JP11471884 U JP 11471884U JP 11471884 U JP11471884 U JP 11471884U JP S6133546 U JPS6133546 U JP S6133546U
Authority
JP
Japan
Prior art keywords
data
transfer device
data transfer
transmitter
receiver
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11471884U
Other languages
Japanese (ja)
Inventor
三智夫 大塚
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to JP11471884U priority Critical patent/JPS6133546U/en
Publication of JPS6133546U publication Critical patent/JPS6133546U/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来装置の一実施例を示す図、第2図と第3図
は従来の装置の信号タイミング関係を示す図、第4図は
従来の装置の欠点を改善する方法を例示した図、第5図
はこの考案の一実施例を示す図、第6図はこの考案にお
ける信号のタイミング関係を示す図である。 図において1はデータ受信機、2はデータ送信機、3は
データ、4はクロツク、5は遅延回路、6は遅延クロツ
クである。 なお各図中同一符号は同一または相当部分を示すものと
する。
FIG. 1 is a diagram showing an example of a conventional device, FIGS. 2 and 3 are diagrams showing signal timing relationships of the conventional device, and FIG. 4 is a diagram illustrating a method for improving the drawbacks of the conventional device. , FIG. 5 is a diagram showing an embodiment of this invention, and FIG. 6 is a diagram showing the timing relationship of signals in this invention. In the figure, 1 is a data receiver, 2 is a data transmitter, 3 is data, 4 is a clock, 5 is a delay circuit, and 6 is a delay clock. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] デイジタルデータを受信するデータ受信機と、デイジタ
ルデータを送信するデータ送信機と、データ送信機から
データ受信機へのデータ転送をシリアルに行うためのク
ロツクを遅延する遅延回路とで構成したことを特徴とす
るデータ転送装置。
It is characterized by being composed of a data receiver that receives digital data, a data transmitter that transmits digital data, and a delay circuit that delays a clock to serially transfer data from the data transmitter to the data receiver. data transfer device.
JP11471884U 1984-07-27 1984-07-27 data transfer device Pending JPS6133546U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11471884U JPS6133546U (en) 1984-07-27 1984-07-27 data transfer device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11471884U JPS6133546U (en) 1984-07-27 1984-07-27 data transfer device

Publications (1)

Publication Number Publication Date
JPS6133546U true JPS6133546U (en) 1986-02-28

Family

ID=30673726

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11471884U Pending JPS6133546U (en) 1984-07-27 1984-07-27 data transfer device

Country Status (1)

Country Link
JP (1) JPS6133546U (en)

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