JPS60136559U - Receiving device for multiplex transmission - Google Patents
Receiving device for multiplex transmissionInfo
- Publication number
- JPS60136559U JPS60136559U JP2508184U JP2508184U JPS60136559U JP S60136559 U JPS60136559 U JP S60136559U JP 2508184 U JP2508184 U JP 2508184U JP 2508184 U JP2508184 U JP 2508184U JP S60136559 U JPS60136559 U JP S60136559U
- Authority
- JP
- Japan
- Prior art keywords
- receiving device
- multiplex transmission
- latch
- signals
- delay means
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Time-Division Multiplex Systems (AREA)
- Amplifiers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は多重伝送システムの説明図、第２図ないし第４
図は本考案の実施例を示し、第２図は多重伝送用受信装
置のブロック図、第３図は復元された出力信号のタイミ
ングチャート、第４図は他の変形例を示すブロック図で
ある。
１・・・多重伝送用受信装置、１２・・・出力遅延手段
、１４ａ〜１４ｄ−・・ラッチ回路、１６・・・ラッチ
信号発生回路。Figure 1 is an explanatory diagram of the multiplex transmission system, Figures 2 to 4
The figures show an embodiment of the present invention, Fig. 2 is a block diagram of a multiplex transmission receiving device, Fig. 3 is a timing chart of a restored output signal, and Fig. 4 is a block diagram showing another modification. . DESCRIPTION OF SYMBOLS 1... Receiving device for multiplex transmission, 12... Output delay means, 14a-14d-... Latch circuit, 16... Latch signal generation circuit.
Claims (2)
元する多重伝送用受信装置において、前記復元された複
数の信号の出力タイミングを順次遅延させる出力遅延手
段を設けたことを特徴とする多重伝送用受信装置。(1) A multiplex transmission receiving device that receives a multiplexed transmission signal and restores it to a plurality of signals, characterized in that an output delay means is provided for sequentially delaying the output timing of the plurality of restored signals. A receiving device for multiplex transmission.
送用受信装置において、前記出力遅延手段は、復元され
た各信号に個別的に対応して設けられた複数のラッチ回
路と、この各ラッチ回路へ順次遅延したラッチ信号を与
えるラッチ信号発生回路とから構成される多重伝送用受
信装置。(2) In the multiplex transmission receiving device according to claim 1 of the utility model registration, the output delay means includes a plurality of latch circuits provided individually corresponding to each restored signal; A multiplex transmission receiving device comprising a latch signal generation circuit that sequentially supplies delayed latch signals to each latch circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2508184U JPS60136559U (en) | 1984-02-22 | 1984-02-22 | Receiving device for multiplex transmission |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2508184U JPS60136559U (en) | 1984-02-22 | 1984-02-22 | Receiving device for multiplex transmission |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60136559U true JPS60136559U (en) | 1985-09-10 |
Family
ID=30519835
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2508184U Pending JPS60136559U (en) | 1984-02-22 | 1984-02-22 | Receiving device for multiplex transmission |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60136559U (en) |
-
1984
- 1984-02-22 JP JP2508184U patent/JPS60136559U/en active Pending
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