JPS6079857U - terminal device - Google Patents

terminal device

Info

Publication number
JPS6079857U
JPS6079857U JP17203083U JP17203083U JPS6079857U JP S6079857 U JPS6079857 U JP S6079857U JP 17203083 U JP17203083 U JP 17203083U JP 17203083 U JP17203083 U JP 17203083U JP S6079857 U JPS6079857 U JP S6079857U
Authority
JP
Japan
Prior art keywords
clock
circuit
terminal device
transmitting
receiving
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17203083U
Other languages
Japanese (ja)
Inventor
正幸 佐々木
Original Assignee
セイコーインスツルメンツ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by セイコーインスツルメンツ株式会社 filed Critical セイコーインスツルメンツ株式会社
Priority to JP17203083U priority Critical patent/JPS6079857U/en
Publication of JPS6079857U publication Critical patent/JPS6079857U/en
Pending legal-status Critical Current

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  • Bidirectional Digital Transmission (AREA)
  • Communication Control (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案のブロック図、第２図は受信データ同期
回路のより詳細な回路、第３図は本発明におけるタイミ
ングチャートである。 ３・・・・・・受信データ同期回路、４・曲・分周回路
、５・・・・・・クロック発生回路、６・・・・・・シ
リアル通信用ＬＳＩ。FIG. 1 is a block diagram of the present invention, FIG. 2 is a more detailed circuit of the received data synchronization circuit, and FIG. 3 is a timing chart of the present invention. 3... Reception data synchronization circuit, 4... Song/frequency dividing circuit, 5... Clock generation circuit, 6... LSI for serial communication.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 外部との送信及び受信可能な端末装置において、少なく
とも受信データを同期化する同期回路と、前記同期回路
の出力でリセットされる分周回路と、前記受信クロック
発生回路へ入力するクロックもしくは送信用クロックを
発生するためのクロック発生回路と、送信用クロックと
受信クロックと受信同期データを入力し送信データを出
力するためのシリアル通信用ト■とから構成されること
を特徴とする端末装置。A terminal device capable of transmitting and receiving external data includes at least a synchronization circuit that synchronizes received data, a frequency dividing circuit that is reset by the output of the synchronization circuit, and a clock input to the reception clock generation circuit or a transmission clock. What is claimed is: 1. A terminal device comprising: a clock generating circuit for generating a clock; and a serial communication port for inputting a transmitting clock, a receiving clock, and receiving synchronization data and outputting transmitting data.
JP17203083U 1983-11-07 1983-11-07 terminal device Pending JPS6079857U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17203083U JPS6079857U (en) 1983-11-07 1983-11-07 terminal device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17203083U JPS6079857U (en) 1983-11-07 1983-11-07 terminal device

Publications (1)

Publication Number Publication Date
JPS6079857U true JPS6079857U (en) 1985-06-03

Family

ID=30375106

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17203083U Pending JPS6079857U (en) 1983-11-07 1983-11-07 terminal device

Country Status (1)

Country Link
JP (1) JPS6079857U (en)

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