JPS5911553U - Serial data transmitter - Google Patents
Serial data transmitterInfo
- Publication number
- JPS5911553U JPS5911553U JP10655582U JP10655582U JPS5911553U JP S5911553 U JPS5911553 U JP S5911553U JP 10655582 U JP10655582 U JP 10655582U JP 10655582 U JP10655582 U JP 10655582U JP S5911553 U JPS5911553 U JP S5911553U
- Authority
- JP
- Japan
- Prior art keywords
- serial data
- data transmitter
- transmitted
- transmission line
- circuit means
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Dc Digital Transmission (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の一実施例による直列データ送信装置の
要部を示すブロック図、第２図は第１図におけるクロッ
ク信号の波形図、第３図は本考案の装置に対応する受信
装置の一例を示すブロック図、第４図は同上送受信装置
の動作例を示す波形図である。
各図中同一部材には同一符号を付し、１０は８ビツトシ
フトレジスタ、１２は２ビツトシフトレジスタ、１４は
伝送路、１６はアンドゲート、１８はＤフリップフロッ
プ、２０は直並列変換回路である。FIG. 1 is a block diagram showing the main parts of a serial data transmitting device according to an embodiment of the present invention, FIG. 2 is a waveform diagram of the clock signal in FIG. 1, and FIG. 3 is a receiving device corresponding to the device of the present invention. FIG. 4 is a block diagram showing an example of the above, and FIG. 4 is a waveform diagram showing an example of the operation of the above transmitting/receiving device. Identical parts in each figure are given the same reference numerals; 10 is an 8-bit shift register, 12 is a 2-bit shift register, 14 is a transmission line, 16 is an AND gate, 18 is a D flip-flop, and 20 is a serial-parallel conversion circuit. be.
Claims (1)
ものにおいて、一定周期のクロック信号を上記伝送路に
常時出力する回路手段と、上記クロック信号のスペース
部に伝送すべきディジタルデータ信号を１ビツトづつ付
加して上記伝送路に出力する回路手段とを備えたことを
特徴とする直列データ送信装置。In a device that outputs a digital data signal in series to one transmission line, circuit means always outputs a clock signal of a constant period to the transmission line, and a digital data signal to be transmitted is transmitted one bit at a time to the space part of the clock signal. 1. A serial data transmitting device characterized by comprising additional circuit means for outputting to the transmission path.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10655582U JPS5911553U (en) | 1982-07-14 | 1982-07-14 | Serial data transmitter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10655582U JPS5911553U (en) | 1982-07-14 | 1982-07-14 | Serial data transmitter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5911553U true JPS5911553U (en) | 1984-01-24 |
Family
ID=30249311
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10655582U Pending JPS5911553U (en) | 1982-07-14 | 1982-07-14 | Serial data transmitter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5911553U (en) |
-
1982
- 1982-07-14 JP JP10655582U patent/JPS5911553U/en active Pending
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