JPS588258U - Receiver jamming remover - Google Patents

Receiver jamming remover

Info

Publication number
JPS588258U
JPS588258U JP10240081U JP10240081U JPS588258U JP S588258 U JPS588258 U JP S588258U JP 10240081 U JP10240081 U JP 10240081U JP 10240081 U JP10240081 U JP 10240081U JP S588258 U JPS588258 U JP S588258U
Authority
JP
Japan
Prior art keywords
circuit
oscillation circuit
common
oscillation
receiver
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10240081U
Other languages
Japanese (ja)
Inventor
福井 久雄
前島 康徳
Original Assignee
ソニー株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ソニー株式会社 filed Critical ソニー株式会社
Priority to JP10240081U priority Critical patent/JPS588258U/en
Publication of JPS588258U publication Critical patent/JPS588258U/en
Pending legal-status Critical Current

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  • Noise Elimination (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例を示すブロック線図、第2図
は本考案の他の実施例を示す回路図、第3図は本考案の
更に他の実施例を示すブロック線図である。 1は受信回路、4a〜4c、  4A〜4Bは付加回路
、5は共通の廠振回路、8は調整手段である。
Fig. 1 is a block diagram showing one embodiment of the invention, Fig. 2 is a circuit diagram showing another embodiment of the invention, and Fig. 3 is a block diagram showing still another embodiment of the invention. be. 1 is a receiving circuit, 4a to 4c and 4A to 4B are additional circuits, 5 is a common vibration circuit, and 8 is an adjusting means.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 受信回路と、該受信回路に対しビート妨害の原因となる
妨害波信号を発生する可能性のある各別の発振回路を必
要とする複数の付加回路とを有する受信機に於いて、上
記複数の発振回路の代りの1個の共通の発振回路と、該
共通の発振回路の発振周波数を調整する調整手段とを設
け、上記共通・の発振回路の発振出力を上記複数の付加
回路に供給するようにすると共に、上記調整手段により
上記共通の発振回路の発振周波数を調整して、該共通の
発振回路よりの上記受信回路に対しビート妨害の原因と
なる妨害波信号の発生を回避するようにして成る受信機
の妨害除去装置。
In a receiver having a receiving circuit and a plurality of additional circuits each requiring a separate oscillation circuit that may generate an interference wave signal that may cause beat disturbance to the receiving circuit, the plurality of A common oscillation circuit is provided instead of the oscillation circuit, and adjustment means for adjusting the oscillation frequency of the common oscillation circuit is provided, and the oscillation output of the common oscillation circuit is supplied to the plurality of additional circuits. At the same time, the oscillation frequency of the common oscillation circuit is adjusted by the adjustment means to avoid generation of an interference wave signal that causes beat disturbance to the reception circuit from the common oscillation circuit. A receiver interference removal device consisting of:
JP10240081U 1981-07-10 1981-07-10 Receiver jamming remover Pending JPS588258U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10240081U JPS588258U (en) 1981-07-10 1981-07-10 Receiver jamming remover

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10240081U JPS588258U (en) 1981-07-10 1981-07-10 Receiver jamming remover

Publications (1)

Publication Number Publication Date
JPS588258U true JPS588258U (en) 1983-01-19

Family

ID=29897038

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10240081U Pending JPS588258U (en) 1981-07-10 1981-07-10 Receiver jamming remover

Country Status (1)

Country Link
JP (1) JPS588258U (en)

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