JPS609333U - PLL receiver - Google Patents

PLL receiver

Info

Publication number
JPS609333U
JPS609333U JP10022683U JP10022683U JPS609333U JP S609333 U JPS609333 U JP S609333U JP 10022683 U JP10022683 U JP 10022683U JP 10022683 U JP10022683 U JP 10022683U JP S609333 U JPS609333 U JP S609333U
Authority
JP
Japan
Prior art keywords
tuning
generating means
tuning signal
signal
response
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10022683U
Other languages
Japanese (ja)
Inventor
喜治 植木
幸弘 金子
Original Assignee
パイオニア株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by パイオニア株式会社 filed Critical パイオニア株式会社
Priority to JP10022683U priority Critical patent/JPS609333U/en
Publication of JPS609333U publication Critical patent/JPS609333U/en
Pending legal-status Critical Current

Links

Landscapes

  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)
  • Noise Elimination (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

図面は本考案の一実施例を示すブロック図である。 6・・・・・・分周器、15・・・・・・同調信号発生
回路、  −17・・・・・・ブザー。
The drawing is a block diagram showing an embodiment of the present invention. 6... Frequency divider, 15... Tuning signal generation circuit, -17... Buzzer.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 同調操作によりPLT回路の分周器の分周比を変えて同
調を行うと共に、該同調操作時に音声ミュートをかける
ようになしたPLL式受信装置であって、前記同調操作
時に放送電波をキャッチしたとき、これは応じて同調信
号を発生する同調信号発生手段と、該同調信号発生手段
からの同調信号に応じて音を発生する同調音発生手段と
を備えることを特徴とするPLL式受信装置。
A PLL type receiving device which performs tuning by changing the frequency division ratio of a frequency divider of a PLT circuit through a tuning operation, and mutes audio at the time of the tuning operation, and which catches broadcast radio waves during the tuning operation. 1. A PLL type receiving device comprising: a tuning signal generating means for generating a tuning signal in response to a tuning signal; and a tuning sound generating means for generating a sound in response to a tuning signal from the tuning signal generating means.
JP10022683U 1983-06-30 1983-06-30 PLL receiver Pending JPS609333U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10022683U JPS609333U (en) 1983-06-30 1983-06-30 PLL receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10022683U JPS609333U (en) 1983-06-30 1983-06-30 PLL receiver

Publications (1)

Publication Number Publication Date
JPS609333U true JPS609333U (en) 1985-01-22

Family

ID=30237193

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10022683U Pending JPS609333U (en) 1983-06-30 1983-06-30 PLL receiver

Country Status (1)

Country Link
JP (1) JPS609333U (en)

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