JPS58155140U - Receiving machine - Google Patents

Receiving machine

Info

Publication number
JPS58155140U
JPS58155140U JP5096082U JP5096082U JPS58155140U JP S58155140 U JPS58155140 U JP S58155140U JP 5096082 U JP5096082 U JP 5096082U JP 5096082 U JP5096082 U JP 5096082U JP S58155140 U JPS58155140 U JP S58155140U
Authority
JP
Japan
Prior art keywords
receiving machine
synthesizer part
intermediate frequency
receiver
switched
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5096082U
Other languages
Japanese (ja)
Inventor
昇 中川
Original Assignee
ソニー株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ソニー株式会社 filed Critical ソニー株式会社
Priority to JP5096082U priority Critical patent/JPS58155140U/en
Publication of JPS58155140U publication Critical patent/JPS58155140U/en
Pending legal-status Critical Current

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Landscapes

  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の受信機の一例を示す回路図、第2図はこ
の考案の一実施例を示す回路図である。 5は第1の中間周波増幅回路、6は第1の沖波器、7は
第2の沖波器、8は第2の中間周波増幅回路、9は検波
器、18は第3の沖波器、28はコレトロール回路、2
9はPLL回路、41はトランジスタ、44は検波器で
ある。
FIG. 1 is a circuit diagram showing an example of a conventional receiver, and FIG. 2 is a circuit diagram showing an embodiment of this invention. 5 is a first intermediate frequency amplifier circuit, 6 is a first Oki transducer, 7 is a second Oki transducer, 8 is a second intermediate frequency amplifier circuit, 9 is a wave detector, 18 is a third Oki transducer, 28 is the cholesterol circuit, 2
9 is a PLL circuit, 41 is a transistor, and 44 is a wave detector.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] シンセサイザ一部を有する受信機において、中間周波段
の広帯域幅及び狭帯域幅を上記シンセサイザ一部のミュ
ーティング出力信号により切り換えるようにしたことを
特徴とする受信機。
1. A receiver having a synthesizer part, characterized in that the wide bandwidth and narrow bandwidth of the intermediate frequency stage are switched by a muting output signal of the synthesizer part.
JP5096082U 1982-04-08 1982-04-08 Receiving machine Pending JPS58155140U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5096082U JPS58155140U (en) 1982-04-08 1982-04-08 Receiving machine

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5096082U JPS58155140U (en) 1982-04-08 1982-04-08 Receiving machine

Publications (1)

Publication Number Publication Date
JPS58155140U true JPS58155140U (en) 1983-10-17

Family

ID=30061734

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5096082U Pending JPS58155140U (en) 1982-04-08 1982-04-08 Receiving machine

Country Status (1)

Country Link
JP (1) JPS58155140U (en)

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