JPS5917653U - receiving device - Google Patents
receiving deviceInfo
- Publication number
- JPS5917653U JPS5917653U JP11056382U JP11056382U JPS5917653U JP S5917653 U JPS5917653 U JP S5917653U JP 11056382 U JP11056382 U JP 11056382U JP 11056382 U JP11056382 U JP 11056382U JP S5917653 U JPS5917653 U JP S5917653U
- Authority
- JP
- Japan
- Prior art keywords
- receiving device
- amplification stage
- frequency amplification
- high frequency
- hetero
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Superheterodyne Receivers (AREA)
- Noise Elimination (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来のスーパヘテロゲイン式受信機の概略構成
を示す回路図、第2図は従来の受信機における高周波増
幅段の同調周波数と、希望受信局との関係を示すグラフ
、第3図は第2図のグラフにおいて、高周波増幅段にお
ける減衰特性を示すグラフ、第4図は本考案に係わる受
信装置の一実施例を示す回路図、第5図は本考案の受信
装置の妨害除去原理を示すグラフ、第6図は受信最良点
サーチ回路を構成するマイクロプロセッサで実行サレる
、システムプログラムの構成を示スフローチャートであ
る。
1・・・PLLシステム、2・・・妨害検出回路、3・
・・受信最良点サーチ回路、4・・・ボリューム、RF
・・・高周波増幅段、MIX・・・混合段、IF・・・
中間周波増幅段、DET・・・検波段、O8C・・・局
部発振器。Figure 1 is a circuit diagram showing the schematic configuration of a conventional super-hetero gain type receiver, Figure 2 is a graph showing the relationship between the tuning frequency of the high-frequency amplification stage and the desired receiving station in the conventional receiver, and Figure 3. is a graph showing the attenuation characteristics in the high frequency amplification stage in the graph of Fig. 2, Fig. 4 is a circuit diagram showing an embodiment of the receiving device according to the present invention, and Fig. 5 is the interference removal principle of the receiving device of the present invention. FIG. 6 is a flowchart showing the structure of a system program executed by the microprocessor constituting the reception best point search circuit. 1...PLL system, 2...disturbance detection circuit, 3.
...Reception best point search circuit, 4...Volume, RF
...High frequency amplification stage, MIX...Mixing stage, IF...
Intermediate frequency amplification stage, DET...detection stage, O8C...local oscillator.
Claims (1)
置の高周波増幅段における同調周波数を、独立して可変
なし得るように構成したごとを特徴とする受信装置。1. A super-hetero gain type receiving device, characterized in that the tuning frequency in a high frequency amplification stage of the receiving device is configured to be independently variable.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11056382U JPS5917653U (en) | 1982-07-21 | 1982-07-21 | receiving device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11056382U JPS5917653U (en) | 1982-07-21 | 1982-07-21 | receiving device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5917653U true JPS5917653U (en) | 1984-02-02 |
Family
ID=30257075
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11056382U Pending JPS5917653U (en) | 1982-07-21 | 1982-07-21 | receiving device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5917653U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01171879A (en) * | 1987-12-26 | 1989-07-06 | Juki Corp | Ink ribbon guide device for printer |
-
1982
- 1982-07-21 JP JP11056382U patent/JPS5917653U/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01171879A (en) * | 1987-12-26 | 1989-07-06 | Juki Corp | Ink ribbon guide device for printer |
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