JPS59147338U - Detuned oscillation prevention circuit - Google Patents

Detuned oscillation prevention circuit

Info

Publication number
JPS59147338U
JPS59147338U JP4033483U JP4033483U JPS59147338U JP S59147338 U JPS59147338 U JP S59147338U JP 4033483 U JP4033483 U JP 4033483U JP 4033483 U JP4033483 U JP 4033483U JP S59147338 U JPS59147338 U JP S59147338U
Authority
JP
Japan
Prior art keywords
circuit
output
oscillation prevention
detuned
prevention circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4033483U
Other languages
Japanese (ja)
Inventor
今川 敏幸
Original Assignee
クラリオン株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by クラリオン株式会社 filed Critical クラリオン株式会社
Priority to JP4033483U priority Critical patent/JPS59147338U/en
Publication of JPS59147338U publication Critical patent/JPS59147338U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は高周波増幅器の利得と周波数の関係を表わすダ
イヤグラム、第2図は本考案による離調発振防止回路を
含むラジオの増幅および検波部分のブロック図である。 1・・・高周波増幅器、2・・・ミキサ回路、3・・・
局部発振器、4・・・第1中間周波増幅器、5・・・第
2中間周波増幅器、6・・・検波回路、7・・・デエン
ファシス回路、8・・・信号検出回路、9・・・倍電圧
整流回路、10・・・電圧保持回路、11・・・NAN
D回路、12・・・スイッチング・トランジスタ、13
・・・低域通過フィルタ、C・・・コンデンサ、VR・
・・可変抵抗。
FIG. 1 is a diagram showing the relationship between the gain and frequency of a high frequency amplifier, and FIG. 2 is a block diagram of the amplification and detection portion of a radio including the detuned oscillation prevention circuit according to the present invention. 1...High frequency amplifier, 2...Mixer circuit, 3...
Local oscillator, 4... First intermediate frequency amplifier, 5... Second intermediate frequency amplifier, 6... Detection circuit, 7... De-emphasis circuit, 8... Signal detection circuit, 9... Voltage doubler rectifier circuit, 10... Voltage holding circuit, 11... NAN
D circuit, 12... switching transistor, 13
・・・Low pass filter, C... Capacitor, VR・
...Variable resistance.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 信号検出回路と、該信号検出回路の出力を整流する整流
回路と、該整流回路の出力電圧を予め定められた時間保
持する電圧保持回路と、上記整流回路の出力および上記
電圧保持回路の出力が入力されるNAND回路と、エミ
ッタが接地され、コレクタが検波回路の後に設けられた
デエンファシス回路にコンデンサを介して接続され、ベ
ースが上記NAND回路の出力に接続されているスイッ
チング・トランジスタとを含み、同調から離調あるいは
その逆の操作時オーディオ信号の中に含まれている高域
成分をアースにバイパスさせることを特徴トスる、μチ
ューナ・ラジオのための離調発振防止回路。
a signal detection circuit, a rectification circuit that rectifies the output of the signal detection circuit, a voltage holding circuit that holds the output voltage of the rectification circuit for a predetermined time, and an output of the rectification circuit and an output of the voltage holding circuit. It includes an input NAND circuit, and a switching transistor whose emitter is grounded, whose collector is connected via a capacitor to a de-emphasis circuit provided after the detection circuit, and whose base is connected to the output of the NAND circuit. A detuning oscillation prevention circuit for μ tuner radios, which bypasses high-frequency components contained in an audio signal to ground when changing from tuning to detuning or vice versa.
JP4033483U 1983-03-18 1983-03-18 Detuned oscillation prevention circuit Pending JPS59147338U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4033483U JPS59147338U (en) 1983-03-18 1983-03-18 Detuned oscillation prevention circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4033483U JPS59147338U (en) 1983-03-18 1983-03-18 Detuned oscillation prevention circuit

Publications (1)

Publication Number Publication Date
JPS59147338U true JPS59147338U (en) 1984-10-02

Family

ID=30170956

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4033483U Pending JPS59147338U (en) 1983-03-18 1983-03-18 Detuned oscillation prevention circuit

Country Status (1)

Country Link
JP (1) JPS59147338U (en)

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