JPS5882052U - Tuner output circuit - Google Patents
Tuner output circuitInfo
- Publication number
- JPS5882052U JPS5882052U JP17599881U JP17599881U JPS5882052U JP S5882052 U JPS5882052 U JP S5882052U JP 17599881 U JP17599881 U JP 17599881U JP 17599881 U JP17599881 U JP 17599881U JP S5882052 U JPS5882052 U JP S5882052U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- tuner
- output circuit
- pass filter
- low
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Filters And Equalizers (AREA)
- Superheterodyne Receivers (AREA)
- Noise Elimination (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来のチューナ出力回路図、及び第2図は本考
案に係るFET混合段を含むチューナの出力回路図であ
る。
1・・・・・−FET(混合段)、2・・・・・・IF
出力端子、13・・・・・・IF複同調フィルタ、14
・・・・・・ローパスフィルタ、21.22・・・・・
・脚部コンデンサ、23・・・・・・中央部インダクタ
、24・・・・・・抵抗(約50〜150Ω)。FIG. 1 is a conventional tuner output circuit diagram, and FIG. 2 is a tuner output circuit diagram including an FET mixing stage according to the present invention. 1...-FET (mixing stage), 2...IF
Output terminal, 13...IF double tuning filter, 14
...Low pass filter, 21.22...
- Leg capacitor, 23...Central inductor, 24...Resistance (approximately 50 to 150Ω).
Claims (1)
FET混合回路の出力側にIF複同調フィルタとローパ
スフィルタとを配設して出力端子からIF倍信号導出す
るチューナにおいて、前記ローパスフィルタはτ形状回
路の脚部コンデンサと中央部インダクタをそれぞれロー
カル発振信号の高調波を減衰するに充分な値に選定して
構成すると共に前記中央部インダクタに抵抗値が約50
〜150Ωの範囲で選定される抵抗を並列接続したこと
を特徴とするチューナ出力回路。MOS that mixes RF input signal and local oscillation signal
In a tuner in which an IF double-tuned filter and a low-pass filter are disposed on the output side of a FET mixing circuit to derive an IF multiplied signal from the output terminal, the low-pass filter locally oscillates the leg capacitors and central inductor of the τ-shaped circuit, respectively. The center inductor has a resistance value of approximately 50 Ω, and is selected to have a value sufficient to attenuate the harmonics of the signal.
A tuner output circuit characterized in that resistors selected in the range of ~150Ω are connected in parallel.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17599881U JPS5882052U (en) | 1981-11-25 | 1981-11-25 | Tuner output circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17599881U JPS5882052U (en) | 1981-11-25 | 1981-11-25 | Tuner output circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5882052U true JPS5882052U (en) | 1983-06-03 |
JPS6325783Y2 JPS6325783Y2 (en) | 1988-07-13 |
Family
ID=29968651
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17599881U Granted JPS5882052U (en) | 1981-11-25 | 1981-11-25 | Tuner output circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5882052U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2017129503A (en) * | 2016-01-21 | 2017-07-27 | 日本電信電話株式会社 | Conduction disturbing wave measurement device |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5020646A (en) * | 1973-06-22 | 1975-03-05 |
-
1981
- 1981-11-25 JP JP17599881U patent/JPS5882052U/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5020646A (en) * | 1973-06-22 | 1975-03-05 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2017129503A (en) * | 2016-01-21 | 2017-07-27 | 日本電信電話株式会社 | Conduction disturbing wave measurement device |
Also Published As
Publication number | Publication date |
---|---|
JPS6325783Y2 (en) | 1988-07-13 |
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