JPS6163127A - Time division multiplex converting integrated circuit - Google Patents

Abstract

PURPOSE:To miniaturize the circuit constitution by using an external clock signal having the same frequency as a frequency-divided clock signal but different in phase to control the phase of the frequency-divided clock signal and the external clock signal to a desired value. CONSTITUTION:When a data terminal device is operated by a clock of a time division conversion LSI30 and the data terminal device transmits a transmission data by using a unique clock where the frequency is coincident but the phase is different, the clock incoming from the data terminal device is used as an external clock and a phase control circuit 38 controls a frequency division circuit 37. In specifying the frequency-divided clock, especially the phase of the clock to a register 40 and the external clock, the data processed by the data terminal device is fetched to the inside of the LSI30 without being mistaken as the internal clock of the LSI30 even when no buffer memory is used.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an improvement of an integrated circuit for time division multiplex conversion used in a master station and a slave station of a local area network system (LAN) or the like.

The number of integrated circuits for time division multiplexing used in the master station and slave stations is 1.
It is desirable to be able to do it in different types.

[Conventional technology]

FIG. 4 is a block diagram showing the circuit configuration of an integrated circuit for time division multiplex conversion of a master station in a conventional example, and FIG. 5 is a block diagram showing a circuit configuration of an integrated circuit for time division multiplex conversion in a slave station of a conventional example. .

1 and 16 in the figure are LS for time division multiplex conversion of the master station and slave station, respectively.
I, 2, 17 are receiving side circuits, 3.18 are transmitting side circuits, 4
, 19 is an S/P converter; 5. ．． 10゜20.25 is a register, 6.11.21 is a distributor, 7.12.22 is a frequency dividing circuit, 8 and 23 are synchronous circuits, 9.24 is a P/S converter,
13 is a synchronization signal output path, 14 is a main clock generator, and 5DATA-H and RDATA-H are high-frequency side transmission data, reception data, TDATA-L, and RDATA, respectively.
・L is transmission data, reception data, and 5CL on the low frequency side, respectively.
K-H and RCLK-H are the transmission clocks on the high frequency side, respectively.
Reception clocks, TCLK-L, and RCLK-L are abbreviations for transmission clock and reception clock, respectively, for receiving and transmitting data to and from a data terminal on the low frequency side, and these abbreviations will be used hereinafter.

The circuit configuration of the conventional integrated circuit for time division multiplex conversion of the main station and the slave station is as shown in FIGS. 4 and 5.
On the main station side, the main clock from the main clock generator 14 is sent to the slave station via the distributor 11 as 5CLK-H, and also to the P/S converter 9 and the frequency divider circuit 12.
2, the frequency is divided into locks as necessary and transmitted as TCLK-L to the P/S converter 9, the register 10, the synchronizing signal sending circuit 13, and the data terminal side.

On the slave station side, 5CLK・H sent from the master station side is R
5CLK-H is received as 5CLK-H to the main station side through the distributor 21, and 5CLK-H is sent to the S/P converter 19. P/S converter 24. and is sent to the frequency divider circuit 22, where the frequency is divided into locks as necessary, and then sent to the P/S converter 24. Register 25. and RCLK/L, TCLK on the data terminal side
-Sent as L.

In addition, 5CLK-H sent from the slave station side to the master station side is received as RCLK-H on the master station side, and sent via the distributor 6 to the S/
It is sent to the P converter 4 and the frequency dividing circuit 7, and the frequency dividing circuit 7
If necessary, the frequency is divided into locks, register 5 and synchronization circuit 8.
and is transmitted to the data terminal side as RCLK-L.

In this way, the clock is transmitted, but the 5
The phases of CLK-H and RCLK-H do not match, and therefore the phases of RCLK-L and TCLK-L on the data terminal side also do not match, and since the functions on the main station side and slave station side are different, the main station The circuit configurations of the time division multiplex conversion LS11 on the side and the time division multiplex conversion LS116 on the slave side are shown in Figures 4 and 5.
They differ as shown in the figure.

In this case, assuming that the data terminals connected to the time division multiplexing LSII or 16 operate on the clock from the time division multiplexing LSII or 16 on the sending and receiving sides, the time division multiplexing LSII or 16 and the data terminal can be connected as is, but if the data terminals are sending out data using their own clocks with the same frequency but different phases, the data terminals on the master station side and the slave side It is possible to insert a buffer memory (elastic store memory) on the transmitting side of the data terminal, write to the memory using the clock on the data terminal side, and read the data in the memory using TCLK-L from LS11.16 for time division multiplex conversion. It becomes necessary.

[Problem that the invention seeks to solve]

As explained above, in the past, the circuit configurations of the time division multiplexing LSIs on the master station side and the slave station side were different, making it impossible to use only one type. If the transmission data is transmitted using unique clocks that match but have different phases, there is a problem that a buffer memory is required on the transmitting side of the data terminal, resulting in a large circuit configuration.

[Means for solving problems]

The above problem is solved by controlling the frequency dividing circuit using an external clock signal that has the same frequency as the divided clock signal but a different phase, and specifies the phase of the divided clock signal and the external clock signal to a desired value. This problem is solved by the integrated circuit for time division multiplex conversion of the present invention.

[Effect]

The present invention solves the problem of transmitting clock (TCLK-L) and receiving clock (RCLK-L) from the master station to the data terminal side, which is a problem when implementing a time division multiplex conversion LSI for the master station and slave station with one type of LSI. In order to prevent data signal errors caused by the phase shift of L), and when the data terminal side is transmitting data using its own clock with the same frequency but a different phase, a buffer is installed on the transmitting side of the data terminal. In order to eliminate the need for memory, the frequency divider circuit of the transmitting side circuit is controlled by an external clock (RCLK-L, clock from the data terminal side), and the phase of the external clock and the clock inside the LSI is adjusted as desired. This makes it possible to specify the value of .

〔Example'〕

FIG. 1 is a block diagram showing the circuit configuration of a time division multiplex conversion LSR according to an embodiment of the present invention, and FIG. 2 is a frequency dividing circuit 3 of FIG. 1.
7 and a block diagram showing the details of the circuit configuration of one example of the phase control circuit 38, FIG. 3 (1) and (2) are time cheats of the waveforms and data of each part of FIG. 2, and (A) to (K) corresponds to point a- in FIG. 2, and (L) indicates data.

In Figure 1, 30 is an LSI for time division multiplex conversion, and 31 is an S/P.
Converter, 32.40 is a register, 33 is a distribution controller, 3
4.37 is a frequency divider circuit, 35 is a synchronous circuit, 36 is a distributor,
38 is a phase control circuit, 39 is a P/S converter, 41 is a synchronization signal sending circuit, 50 in FIG. 2 is a basic 10 frequency divider circuit, 51
is a phase control circuit, 52 is a differential circuit, 53 to 61 are FFs,
Reference numerals 62 to 65 indicate OR circuits, and 66 indicates a NOR circuit, and the same reference numerals throughout the drawings indicate those having the same function.

When the circuit shown in FIG. 1 is used for the main station, the distribution controller 33 is configured to receive and receive the clock from the main clock generator 14 using a control signal, and this clock is transmitted to the S/P converter 3 and 2. 39 and also sends it to the slave station as 5CLK-H.

Here, assuming that the data terminal operates with the clock of the time division multiplex conversion LSI 30, the data terminal side only needs to operate with TCLK-L from the frequency dividing circuit 37, and the phase control circuit 38 is not used. If the data terminal side is transmitting data using its own clock that has the same frequency but a different phase, the phase control circuit 38 uses the clock that is raised from the data terminal side as the external clock. Controls the frequency dividing circuit 37 (this control will be described later)
By specifying the phase of the frequency-divided clock, especially the clock to the register 40, and the external clock, data processed on the data terminal side can be transferred to the LSI 3 without using a buffer memory.
It can be loaded into the LSI 30 without error using an internal clock of 0.

When used as a slave station, the distribution controller 33 is set to receive RCLK-H using a control signal, and this clock is sent to the S/P conversion converter 3 public 1S converter 39 and the main station side with 5CLK-H. Transmit H.

Here, assuming that the data terminal operates with the clock of the time division multiplex conversion LSi 30, RCLK-L from the frequency dividing circuit 34 is sent to the data terminal side and used as an external clock by the phase control circuit 38. control 37,
If you specify the phase of the frequency-divided clock, especially the clock to the register 40, and the external clock, the data processed on the data terminal side with RCLK-L can be output from the frequency divider circuit 37 to the register 40. Same TCLKL
will be processed without error.

If the data terminal side is transmitting data using its own clock that has the same frequency but a different phase, use
Instead of using LK-L as the external clock, use the clock coming from the data terminal as the external clock,
If the phase control circuit 38 controls the frequency dividing circuit 37 and specifies the phase of the divided clock, especially the clock to the register 40, and the external clock, the data processed on the data terminal side can be processed without using a buffer memory. It can be taken into the LSI 30 without error using the internal clock of the LSI 30.

Therefore, the time division multiplex conversion LSI is used as F for master station and slave station.
If the data terminal side is transmitting data using its own clock that has the same frequency but a different phase, there is no need for a buffer memory on the transmitting side of the data terminal, simplifying the circuit. You can.

Next, the phase control circuit 38 receives the RCLK from the frequency dividing circuit 34.
-L is input as an external clock, and the case where the phase with TCLK-L from the frequency divider circuit 37 is specified will be explained using FIG. 2 and FIG. 3 as an example.

(K) in Fig. 3 (1) (2) from the distributor 36 in Fig. 1
The 5CLK-H shown in FIG.
) The external clock (RCLK-L) shown in (A) is input to FF60 of the differentiating circuit 52, and 5C
The external clock is punched out at LK-H and aligned to the phase of 5CLK-H, resulting in the waveforms shown in FIGS. 3(1), 3(B) and 3(C).
), it becomes a 1-bit width negative pulse of 5CLKH as shown in (D), and is input to the OR circuit 63 of the phase control circuit 51, and the output is 5CLK as shown in (E) of FIG. 3(1).
-H has a negative pulse waveform of 1/2 bit width, and FF5
Connect manually to the clock terminal of 9.

On the other hand, the FF 53 whose frequency is divided by 10 by the basic 10 frequency divider circuit 50 ~
The outputs of 57 are (F), (G), and (H) in Figure 3 (2), respectively.
(1) As shown in (J), the Q output of FF 55 and the Q output of FF 56 are transferred to a specific position of the basic lO frequency divider circuit 50 by the NOR circuit 66 as shown in (H) of FIG. 3 (2). So 5
Create a 1-bit width positive pulse of CLK-H and input it to the FF59, (E) in Figure 3 (1) and (E) in Figure 3 (2).
If the output of the FF 59 is at L level, the OR circuit 62. A shift circuit constituted by the FF 58 causes the 10 frequency divider to operate as an 11 frequency divider.

When the above operation is repeated and the output of FF59 becomes H level (phase control completed), the frequency divider circuit divides the frequency by 10 and outputs the external clock shown in (A) of FIG. 3(1)(2) and
The phase relationship with the clock of 5CLK-H shown in (F) of 2) is as shown in FIG. .

If this happens, the data shown in FIG. 3 (2) and (L) processed by the external clock (RCL K・L) will be
Processing can be performed without error using TCLK-L shown in (F) of 2).

〔Effect of the invention〕

As explained in detail above (according to the present invention, it is possible to use one type of integrated circuit for time division multiplex conversion for the master station and slave station, and the data terminal side has the same frequency but a different phase. When transmitting data is transmitted using a unique clock, there is no need for a buffer memory on the transmitting side of the data terminal, which has the effect of reducing the size of the circuit configuration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the circuit configuration of an integrated circuit for time division multiplex conversion according to an embodiment of the present invention, and FIG. 2 is a detailed circuit configuration of an example of the frequency divider circuit 37 and phase control circuit 38 in FIG. 1. Block diagram showing Figure 3 (1)
(2) is a time cheat of the waveforms and data of each part in Fig. 2, Fig. 4 is a block diagram showing the circuit configuration of the integrated circuit for time division multiplex conversion of the main station in the conventional example, and Fig. 5 is in the conventional example. FIG. 2 is a block diagram showing a circuit configuration of a time division multiplex conversion integrated circuit of a slave station. In the figure, 1.16.30 is an integrated circuit for time division multiplex conversion, 2.17
is the receiving side circuit, 3.18 is the transmitting side circuit, 4.19.31 is the S/P converter, 5.10, 20.25.32.37 is the register, 6.1
1, 21.36 is a distributor, ? , 12.22, 34.37 are frequency dividing circuits, 8.23.3
5 is a synchronization circuit, 9.24.39 is a P/S converter, 13.41 is a synchronization signal output path, 14 is a main clock ordering device, 33 is a distribution controller, 38.51 is a phase control circuit, 50 is a Basic 10 frequency divider circuit, 52 is a differentiation circuit, 53 to 61 are FFs. 62 to 65 are OR circuits, and 66 is a NOR circuit. 1 translation Qin 4 eyes Qin 5 mouth

Claims (1)

[Claims] In a time division multiplexing integrated circuit having a function of dividing a clock signal by a frequency dividing circuit and processing a data signal using the divided clock signal, the integrated circuit has the same frequency as the divided clock signal but a different phase. An integrated circuit for time division multiplex conversion, comprising means for controlling the frequency dividing circuit using an external clock signal and specifying the phases of the frequency-divided clock signal and the external clock signal to desired values. .