JPH03133226A - Frame phase synchronization circuit - Google Patents

Abstract

PURPOSE:To attain efficient data transmission by using the delay output of a reception data corresponding to a phase difference without passing through a RAM when the phase difference between a reference frame signal and a reception frame signal is coincident or several bits. CONSTITUTION:The output data of a FF 1 fetching a reception data 1 is delayed sequentially by 0-n and outputted by an n-bit shift register 9 and a selector 11 is provided, which selects one of the input of the shift register 9 and n-bit outputs among total (n+1) signals. A phase difference detection circuit 10 detects whether the reception frame signal and the reference frame signal are coincident in the phase or different from several bits, the selector 11 selects the bit output corresponding to the bit deviation by the shift register 9.

Description

Detailed Description of the Invention Technical Field The present invention relates to a frame phase synchronization circuit, and particularly to a loop type L
The present invention relates to a frame phase synchronization circuit for aligning the phases of a transmitted frame and a received frame in a master station such as an AN (local area network) device.

In a conventional loop type LAN device, each slave station synchronizes frame signals from a master station and performs processes such as detecting address signals and transmitting and receiving data.

In order to transmit the received data signal from the slave station onto the network again, the master station needs to transfer the received data signal to the reference transmission frame of the master station. For this purpose, a circuit is required to achieve phase synchronization between the reference transmission frame signal and the reception frame signal.

In a conventional frame phase synchronization circuit of this type, first, an elastic store circuit is used for the received data to absorb bit phase fluctuations and synchronize the received data with the transmission clock. Next, the received data is sent to the RA in half a bit of the clock using an address synchronized with the received frame signal.
M is written, and the next half bit is read out from the RAM at an address synchronized with the reference frame signal. By doing so, it is possible to phase-synchronize the received data with the basic frame signal.

FIG. 2 is a circuit diagram of such a phase locked circuit.

Received data is sequentially taken into an FF (flip-flop) 1 in synchronization with a reference clock, and this received data is written into a RAM 2 in synchronization with the reference clock.

The write address of this RAM 2 is generated by the write address counter 6. This write address counter 6
is set to 0° each time a received frame signal arrives, and gradually counts up the reference clock.

The read address of the RAM 2 is generated by a read address counter, and is set to "0" each time a reference frame signal arrives, and the reference clock is sequentially counted up. These two addresses are alternately switched by the address selector 5 every half bit of the reference clock and used as read/write addresses of the RAM 2.

Therefore, received data signals are sequentially written into the RAM 2 at write addresses in synchronization with the receive frame signal, and sequentially read out at read addresses in synchronization with the reference frame signal.

Incidentally, the inverting circuit 8 and the FF 3.4 are used for phase matching of the output timing of the RAM 2.

In such a conventional frame phase synchronization circuit, the received data is written on the RAM and then read out, so when the received frame phase matches the reference frame signal phase, or when there is a difference of several bits, Even in the case of a frame signal, the phase is delayed until the next frame signal, resulting in a delay time of one frame or more. Therefore, loop-type LAN devices having a long frame time have the disadvantage that transmission delay time increases and data transmission efficiency decreases.

Structure of the Invention The frame phase synchronization circuit according to the present invention includes a phase difference detection means for detecting a phase difference between a reference frame signal and a received frame signal, and a phase difference detection means for detecting a phase difference between a reference frame signal and a received frame signal, and a phase difference detection means for detecting a phase difference between a reference frame signal and a received frame signal, and a phase difference detecting means for detecting a phase difference between a reference frame signal and a received frame signal, It is characterized by including a delay means for sequentially delaying and outputting for a time, and a selection means for selectively deriving delayed data from the delay means according to the phase difference detected by the phase difference detection means. .

Example Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention, and parts equivalent to those in FIG. 2 are designated by the same reference numerals.

The difference from the conventional example in Fig. 2 is that the F
An n-bit shift register 9 that sequentially delays the output data of the FI by an amount equivalent to 0-n (n is an integer greater than or equal to 1) and outputs the delayed data.
A selector 1 selects one of a total of n+1 signals of the human input and n-bit outputs of the shift register 9.
1.

Furthermore, a phase difference detection circuit 10 is added as a selection control signal for the selector 11, which detects the phase difference between the received frame signal and the reference frame signal, and the selector 11 selects the n+1 signals according to the detected phase difference. One of the signals is selected.

This phase difference detection circuit 10 detects the difference between the received frame signal and the reference frame signal by detecting the difference between the addresses of the write address counter 6 and the read address counter 7. However, the present invention is not limited to this, and the difference between the two frame signals may be directly detected.

The other configurations are the same as the example shown in FIG. 2, and therefore the description thereof will be omitted.

FIG. 3 is an example of a time chart showing the basic operation of the frame phase synchronization circuit according to the present invention, and this example shows a case where the phase difference between the received frame signal and the reference frame signal is 3 bits. .

In such a configuration, received data is taken into the FFI by the base clock and supplied to the data input section of the RAM 2. This RAM 2 stores data according to the write address in half bits of the reference clock, and reads out data in the next half bit according to the read address.

The conventional example shown in FIG. 2 shows that the received data can be synchronized with the reference frame signal by generating the write address and the read address in the address counters 6 and 7 which are synchronized with the received frame signal and the reference frame signal, respectively. As stated above.

FIG. 3 shows the situation at this time. For example, the RAM
The received data DO written in the RAM 2 is read out from the RAM 2 at the read address 0 which is synchronized with the reference frame signal, and is therefore phase-synchronized with the reference frame signal.

In the conventional frame phase synchronization circuit, even if the phase of the received frame signal matches the reference frame signal, since the data is written to and read from the RAM 2, the signal is output with a delay of one frame. Furthermore, even if the phases do not match completely, if there is a shift of several bits, there will be a delay of a period equal to the addition of these several bits to one frame.

Therefore, in the present invention, the phase difference detection circuit 10 detects whether the phases of the received frame signal and the reference frame signal match or are shifted by several bits. The received data) is selected by the selector 11, and if there is a shift of several bits, the bit output corresponding to the number of bit shifts of the shift register 9 (in the case of a one bit shift, the Q of the shift register 9 is selected.
O small output is selected.

By doing so, the received data can be immediately retrieved in synchronization with the reference clock without going through the RAM 2, so that delays of one frame or more can be eliminated compared to the conventional method.

If the number of bits of the shift register 9 is n-8, the phase difference between the reference frame signal and the received frame signal can be up to 8 bits, and the number n can be selected as appropriate.

Effects of the Invention As described above, according to the present invention, if the phase difference between the reference frame signal and the received frame signal is the same or a difference of several bits, reception corresponding to the phase difference can be performed without going through the RAM. Since the delayed output of data is used, it is possible to eliminate approximately one frame of wasted time, and this has the effect of enabling efficient data transmission.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a diagram showing a conventional frame phase synchronization circuit, and FIG. 3 is a time chart showing the basic operation of the frame 10 synchronization circuit. Explanation of symbols of main parts 2...RAM 6.7...Address counter 9...Shift register 10...Phase difference detection circuit 11... ··selector

Claims (1)

[Claims] (1) A phase difference detection means for detecting a phase difference between a reference frame signal and a received frame signal, and a delay means for sequentially delaying received data by an amount corresponding to 0 to n bits (n is an integer of 1 or more) and outputting the delayed data. , and selection means for selectively deriving delay data from the delay means according to the phase difference detected by the phase difference detection means.