JPH05102950A - Phase absorbing device - Google Patents

Abstract

PURPOSE:To inexpensively obtain the device having high reliability by latching necessary data at a prescribed timing conforming to a frame of input data, further delaying this latch data for a prescribed time and latching it, and selecting an abstract object in accordance with a phase difference of an input timing to a latch timing. CONSTITUTION:Input data 10 is subjected to S/P conversion by a shift register 1. A latch timing generating circuit 6 receives an input clock 11 and a frame synchronizing signal 12, and generates a latch signal for a latch 2 and a latch signal for a latch 3 delayed by a half frame period portion from the former. A selector control circuit 8 monitors a latch timing and a load timing by a synchronizing phase detecting part 8A, and in the case both of them are too near, a selecting signal output of a switching signal generating part 8B is switched, and an output of the latch 2 or 3 is outputted as serial data 13 subjected to phase absorption and speed conversion. In such a way, the device having high reliability can be constituted at a low cost.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase absorption device including speed conversion required when connecting the inside and the outside of communication equipment using digital communication means.

[0002]

2. Description of the Related Art When exchanging data, it is necessary to adjust them when the data transmission speed is slightly different between the other party as an input / output object and the self, or when the phases are not in a synchronous relationship. There is.

Conventionally, as a circuit for performing these adjustments, a serial input / output type FIFO (First) is used.
An In First Out element or a dual port memory is used to temporarily store data in these elements and read the data at the same timing for adjustment.

That is, the FIFO element is a buffer element that sequentially stores data and reads data sequentially from the previous storage element. When the FIFO element is used, the transmitted data is sequentially stored. It is possible to match the speed conversion and the phase by storing the data in this FIFO element and reading it according to the speed and phase of the receiving side, but in this case, all the sent data are stored,
Moreover, all the stored data is also read.

Therefore, even unnecessary data is stored in the FIFO element, which is wasteful. That is, when the FIFO element is used, all the transmitted data is stored in the FIFO element, while the storage capacity of the FIFO element is the optimum amount determined by the balance between the received data amount and the read data amount. Therefore, since unnecessary data is also stored, it becomes necessary to secure an unnecessary storage capacity, resulting in unnecessary cost increase of the device.

To solve this, a dual port
It is possible to use memory. This is dual
All the data that is sent is stored and read is necessary from the stored data by utilizing the fact that writing and reading of data, which is a characteristic of the port memory, can be performed in parallel. By picking up something like that, and writing new received data into the storage area of the read data and the storage area of the unnecessary data, by controlling the writing and reading successfully,
The storage capacity can be suppressed to be smaller than that of the FIFO. However, the dual port memory requires address control, and the circuit becomes large.

[0007]

As described above, when data is exchanged, a circuit for adjusting the transmission / reception destinations and the self when the transmission speeds are different or the phases are not matched. However, the conventional circuit for that purpose uses a FIFO element for buffering,
It was configured to buffer using dual port memory.

In the case of the structure using the FIFO element, since all the data is taken in,
Uselessly large FIFO memory elements must be used, and address control must be performed when using dual port memory.

Therefore, in the former case, since it is necessary to allocate the storage capacity to store unnecessary data, there is a waste of the storage capacity that must be secured,
There is a problem that the cost of the useless system is increased, and in the latter case, there is a problem that the complexity of address control and the increase of the circuit scale remain.

Therefore, the object of the present invention is to
It is an object of the present invention to provide a phase absorption device including a speed conversion function that enables a speed conversion and phase absorption without using a large-capacity memory and can be an inexpensive and highly reliable system.

[0011]

In order to achieve the above object, the present invention is configured as follows. That is, in a phase absorption device that takes in input data that is serially transmitted in a frame structure, outputs the output data to the output side in phase with the transmission frame on the output side, parallel data conversion means for converting the input data into parallel data, and The first latch means for holding and outputting the parallel data converted by the parallel data converting means at a predetermined timing according to the frame of the input data, and the data held by the first latch means are stored in the first latch means. A time period within the frame period of the input data from the holding timing of the latch means, and holding and outputting at a timing delayed by a predetermined time during which the held data of the first latch means is in a stable state; 2 latch means, selection means for extracting output data of one of these latch means, and this selection means A serial data conversion unit that fetches the extracted output data at a predetermined timing that matches the frame timing on the output side, converts the output data into serial data, and outputs the serial data in synchronization with the transmission timing on the output side; And a control means for designating an extraction target of the selection means according to a phase difference between the latch timing of the latch means and the fetch timing of the serial data conversion means.

[0012]

In the above structure, the parallel data conversion means converts the input data into parallel data when the input data serially transmitted in the frame structure is fetched and output to the output side in phase with the transmission frame on the output side. However, the parallel data converted by the parallel data conversion means is latched by the first latch means at a predetermined timing according to the frame of the input data. Further, the data held in the first latch means is held by the second latch means for a predetermined time from the data hold timing of the first latch means (within the frame period of the input data from the hold timing of the first latch means). And the data held by the first latch means is delayed by a predetermined time corresponding to a stable time, for example, about a half cycle of the frame cycle of the input data).
Then, the selection means extracts one of the output data of the latch means, and the serial data conversion means fetches the output data extracted by the selection means at a predetermined timing matched with the frame timing of the output side to obtain the serial data. And output in synchronization with the transmission timing on the output side.

On the other hand, the control means designates the extraction target of the selection means according to the phase difference between the latch timing of the first and second latch means and the fetch timing of the serial data conversion means. As a result, the selecting means responds to the phase difference between the latch timing of the first and second latch means and the fetch timing of the serial data converting means. For example, if the phase difference is a small difference on the one hand, the phase difference is sufficient. The output data of one of the latch means is extracted, and when there is sufficient phase difference, any one or the output data of the first latch means is extracted.
The data is given to the serial data conversion means and converted into serial data and output to the output side.

As described above, according to the present invention, the input data is parallel data, and only the necessary data is latched in the parallel data. In order to eliminate the timing at which data transfer is impossible due to the close frame phase difference between the input and output, the previous latch data is further shifted by a half cycle of the input side frame cycle and latched. According to the difference between the output side frame phase and the latch timing phase, for example, the latch data on the side where a sufficient phase difference can be secured is used to restore these two latch data to serial data. This eliminates the need for FIFO elements that need to secure sufficient capacity, memory circuits that require address control, etc., and simplifies the configuration to enable low-cost system configuration, and also provides highly reliable data rate conversion and phase absorption. It is possible to provide a phase absorber capable of

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes an input shift register, which is transmission or reception data (input serial data 10).
Is a register for sequentially taking in and shifting the data into parallel data. 2 and 3 are latches. Of these, the latch 2 receives and holds the data converted in parallel by the input shift register 1, and the latch 3 receives and holds the data held by the latch 2.

Reference numeral 4 is a selector for selecting and outputting the latch data of either the latch 2 or the latch 3. Reference numeral 5 denotes an output shift register, which takes in parallel latched data output via the selector 4 by a load signal from a shift register load timing generation circuit described later and synchronizes with the clock 14 on the output side. The shift operation is performed and the data is converted into serial data and output. The output of the output shift register 5 becomes output serial data that has undergone speed conversion and phase absorption.

Reference numeral 6 is a latch timing generating circuit for generating timing signals such as latch timing for the latches 2 and 3. The latch timing generating circuit 6 uses the input clock 11 and each signal of the input frame (frame synchronization signal) 12 for latch 2 and latch 3 at a timing of a predetermined clock in a predetermined time slot. If a latch signal is output, and the number of time slots per frame is 32 slots and the number of clocks per time slot is 8 clocks, for example, the latch signal generation timing for the latch 2 is n time. At the 7th clock of the slot (8th clock in the time slot), the latch signal generation timing for the latch 3 is (32/2) + n 7th clock of the time slot (8 clocks in the time slot). Clock).

That is, in the circuit of FIG. 1, if there are n time slots per frame, n sets are prepared, each of them is dedicated to another time slot, the data of the time slot of its own is latched, and the speed conversion, The phase is absorbed and output.

Then, the latch timing generation circuit 6 outputs a latch signal at the end timing of the time slot targeted by itself and at the end timing of the time slot separated by a half frame period, and the latch 2 and the latch 3 mutually output the latch signal. The data in the time slots separated by a half frame period is latched, and the data is controlled to be retained for the period of one frame period.

Reference numeral 7 denotes a shift register load timing generation circuit, which is synchronized with the clock 14 on the output side and the frame synchronization signal 15 on the output side and is transferred to the output shift register 5 at the timing immediately before the corresponding time slot period. The load signal is generated.

A selector control circuit 8 is composed of a synchronous phase detecting section 8A and a selector switching signal generating section 8B. The synchronous phase detecting section 8A shifts the latch signal from the latch timing generating circuit 6 and shifts. register·
It receives load signals from the load timing generation circuit 7 and detects the phase state based on these signals (for example,
It is a circuit having a function of detecting a phase difference), and based on this, the selector switching signal generator 8B outputs a selection signal designating a latch to be selected by the selector 4 among the latches 2 and 3. This selector control circuit 8
Thus, the selector 4 selects one of the outputs of the latches 2 and 3 and supplies it to the output shift register 5.

Next, the operation of the present apparatus having such a configuration will be described. Here, as an operation example, the transmission speed is 2.048 MHz.
The case where the data in the time slot “0” of the data transmission frame of is converted into the data of the transmission speed of 64 kHz and the phase is absorbed. The data transmission here has a frame period of 8 kHz and is divided into 32 time slots per frame, and 8 bits of data can be transmitted per one time slot. In this case, the data of the transmission rate of 2.048 MHz in the time slot “0” is converted into the data of the transmission rate of 64 kHz, the phase is absorbed, and the data is output.

FIG. 2 shows the timing on the input side, and FIG. 3 shows the timing on the output side. In FIG. 2, (a) is a clock signal, (b) is a synchronization signal of a transmission frame of transmission data on the input side, and (c) is input data. Further, (d) is a latch timing signal of the latch 2, (e) is a latch timing signal of the latch 3, (f) is a latch data output of the latch 2, and (g) is a latch data output of the latch 3. Also,
In FIG. 3, (a) is a clock signal, (b) is a parallel data load timing of the shift register 5,
(c) is output data from the shift register 5, which is output data after speed conversion and phase absorption.

Explaining with reference to these timing charts, the serial input data 10 is sequentially converted into parallel data by the shift register 1. That is,
The serial input data 10 is sequentially shifted and converted into parallel data by the shift register 1 that operates in synchronization with the 2.048 MHz clock.

On the other hand, the latch timing generation circuit 6 receives a clock 11 of 2.048 MHz which is an input clock and a frame synchronization signal 12 which is a synchronization signal of an input frame,
A latch signal for latch 2 is generated every 8th clock of time slot "0" in synchronization with the frame synchronization signal 12, and a latch signal for latch 3 is output every 8th clock of time slot "16". To do.

That is, the latch signal for the latch 3 (latch timing Q) is generated with a delay of a half frame period from the latch signal for the latch 2 (latch timing P), and the latch 2 holds the latch 3 The data in the time slot “0” will be held with a half frame cycle delay. Since each of the latch timing P and the latch timing Q corresponds to one frame period, the latch 3 holds the data in the time slot “0” with a half frame period shift from the latch 2. become.

As described above, the latch signal from the latch / timing generation circuit 6 having the above timing relationship is received, and the latch 2 latches the output parallel data of the input shift register 1 at the timing when the latch signal is received. The latch 3 holds the latch data of the latch 2 and holds the data for a time corresponding to one frame. And
Under the control of the selector control circuit 8, the selector 4 selects one of the data held in the latches 2 and 3 and sends it to the output shift register 5.

On the other hand, on the output side, the output of the selector 4 is loaded into the output shift register 5 (parallel data) by the load signal generated by the shift register load timing generating circuit 7. As a result, the data of the time slot “0” fetched at the input side is transferred to the output shift register 5, and the output shift register 5 performs serial conversion in synchronization with the 64 kHz clock,
Output as serial data.

Since the load signal output from the shift register load timing generating circuit 7 is synchronized with the frame synchronizing signal 15 and the clock signal 14 on the output side, the load signal is transmitted in synchronization with the frame on the output side. The speed will be 64kHz serial data, and the output data with phase absorption and speed conversion will be obtained.

In the present apparatus, the selector 4 outputs the data of the latch 2 and the data extracted from the input data from the latch 2 and the latch 3 by the output of the selector control circuit 8 (the output of the selector switching signal generator 8B). Or the output of the latch 3 is determined.
Timing R is latch timing P and Q on the input side
If they are far enough apart, it does not matter which data is selected and velocity conversion and phase absorption can be performed.

Therefore, in this case, the selector switching signal generator 8B of the selector control circuit 8 is set to output a selection signal for selecting the output of the latch 2 to the selector 4, for example, so that the output of the latch 2 is output. Can be selected. This can be realized by providing a configuration in which the selection signal for selecting the output of the latch 2 is generated when the in-phase detection unit 8A detects that they are not in phase.
It is also possible to adopt a configuration in which the latch 3 is selected in the same manner.

Now, it is assumed that the load timing R (load signal generation timing) is sufficiently close to the latch timing P (latch signal generation timing) for the latch 2.

In this case, if the input data 10 is currently output as the output serial data 13 by flowing through the input shift register 1 → latch 2 → selector 4 → output shift register 5, the input shift register 1 causes The latch timing at which the parallel-converted data is latched by the latch 2 is R, and the latched data is given to the output shift register 5 via the selector 4,
The output shift register 5 takes in the latch data at the load timing R which is close to the latch timing R in terms of timing. However, since the parallel data is changing in the latch 2, the data applied to the output shift register 5 is also changing, and as a result, the data loaded in the output shift register 5 may be undefined.

Therefore, in the selector control circuit 8, the synchronous phase detector 8A monitors the latch timing P and the load timing R, and when they are too close to each other, the selection signal output of the selector switching signal generator 8B is switched. , Thereby switching the output of the selector 4 from the output of the latch 2 to the output of the latch 3 so that the input data 10 flows through the input shift register 1 → the latch 2 → the latch 3 → the selector 4 → the output shift register 5. , So that the output serial data 13 that has undergone phase absorption and speed conversion is output.

That is, although the data held by the latch 2 is changing, the data held by the latch 3 is obtained from the latch 2 when half a frame time has elapsed after the latch 2 held the data. It holds data,
Since the holding period of each of the latches 2 and 3 is equivalent to one frame time of the transmission frame on the input side, it holds the data when the latch 2 is in a stable state, and
The data of the latch 3 is also stable.

Then, the data held in the latch 3 is fetched by the selector 4 and given to the output shift register 5, so that the data in the time slot "0" on the input side at the transmission rate of 2.048 MHz is set at the transmission rate of 64 kHz. It can be converted to data, phase-absorbed, and output.

Similarly, when the load timing R is too close to the latch timing Q for the latch 3, the selector control circuit 8 controls the switching so that the selector 4 selects the output of the latch 2, so that Input data 1
0 is an input shift register 1 → latch 2 → selector 4 →
It is controlled so as to flow to the output shift register 5 and output as the output serial data 13 which has been subjected to phase absorption and speed conversion.

When the input data 10 flows through the input shift register 1 → latch 2 → selector 4 → output shift register 5 to become the phase-absorbed and speed-converted output serial data 13, the data is 1. Output with data delay less than frame.

On the other hand, when the input data 10 is output in the order of input shift register 1 → latch 2 → latch 3 → selector 4 → output shift register 5, the data is 1 frame or more and less than 2 frames. Data delay occurs. However, this method has a simple structure and
You can surely convert the speed of data and absorb the phase.

The in-phase detector 8A of the selector control circuit 8 determines whether or not the load timing R and the latch timing P or Q are too close to each other. , It should be set appropriately considering the system specifications.

The present invention is not limited to the embodiments described above and shown in the drawings, but can be carried out by appropriately modifying it within the scope not changing the gist of the invention. The timing is set to be delayed by a half cycle of the input side transmission frame cycle with respect to the latch timing of the latch 2, but the present invention is not limited to this, and the point is that even when one side is in an unstable data state, the other side It is only necessary to secure an operation timing that is in a stable state.

Further, for example, the following may be considered as a modification of the present invention. That is, a plurality of output shift registers 5 are prepared to make a plurality of time slots of the input data 10 a plurality of outputs in synchronization with the clock 14 and the frame synchronization signal 15 on the output side, a selector 4, an output shift register 5, and a shift register.・ Preparing multiple load timing generation circuits 7 and selector control circuits 8
A single or a plurality of time slots of the input data 10 is output in synchronization with a clock of an individual phase, or a plurality of series of serial input data 10, 10a, 10b ... Synchronized with the input side clock 11 and the frame synchronization signal 12 Are input to a plurality of input shift registers 1, 1a, 1b ... Corresponding to, all of them are converted into parallel data, and the number of bits of the latch 2, the latch 3, the selector 4, and the output shift register 5 are adjusted to them. Then, it becomes possible to adopt a configuration in which data is multiplexed.

As described above, since only the necessary data and the minimum necessary latches are used, the data is converted by the small number of gates and the data is transmitted and received with different transmission speeds, and the data is absorbed. Can be given and received.
Further, there is an advantage that the design can be made without paying attention to the input clock frequency and the output clock frequency.

As described above, in the present system, in the phase absorber for taking in the input data serially transmitted in the frame structure and outputting the same to the output side in phase with the transmission frame on the output side, the input data is converted into parallel data. To parallel data conversion means, first latch means for holding and outputting the parallel data converted by the parallel data conversion means at a predetermined timing in accordance with a frame of input data, and the first latch. One of the second latch means for holding and outputting the data held by the means with a delay from the data holding timing of the first latch means by about a half cycle of the frame period of the input data, and one of these latch means. The selecting means for extracting the output data and the output data extracted by the selecting means are used for the frame timing on the output side. And a serial data conversion means for converting the data into serial data and outputting the data in synchronization with the transmission timing on the output side, and the serial data conversion means for the latch timing of the first and second latch means. And a control means for designating an extraction target of the selection means according to the phase difference of the capture timing of the.

In such a structure, when the input data serially transmitted in the frame structure is fetched and output to the output side by aligning the phase with the transmission frame on the output side, the parallel data conversion means parallelizes the input data. The data is converted into data, and the parallel data converted by the parallel data conversion means is latched by the first latch means at a predetermined timing according to the frame of the input data, and is held by the first latch means. The data is latched by the second latch means with a delay of about a half frame cycle of the frame cycle of the input data from the latch timing of the first latch means, and the selecting means has one of these latch means. One of the output data is extracted, and the serial data conversion means is extracted by this selection means. Incorporation at a prescribed timing to output data to the frame timing of the output side, are those referred synchronization with is output to the transmission timing of the output side is converted into serial data.

Further, the control means is made to designate the extraction target of the selection means according to the phase difference between the latch timing of the first and second latch means and the fetch timing of the serial data conversion means. ..

As a result, the selection means has the first and second selection means.
According to the phase difference between the latch timing of the latch means and the fetch timing of the serial data conversion means, for example,
Assuming that the phase difference is a small difference on the one hand, the output data of the latch means having the sufficient phase difference is extracted, and if there is a sufficient phase difference, any one or the first
The output data of the latch means can be extracted, given to the serial data conversion means, converted into serial data, and output to the output side. Of the latch data, the latch data on the stable side can be given to the serial data conversion means to output the serial data. It can be converted and output to the output side.

As described above, according to the present invention, the input data is parallel data, and only the necessary data is latched in the parallel data, and since the frame phase difference between the input and output is close, the timing at which data transfer is impossible is eliminated. The previous latch data is further shifted by about a half cycle of the input side frame period so as to be latched. For example, a sufficient phase difference is secured between these two latch data depending on the difference between the output side frame phase and the latch timing phase. This means that the latch data on the working side is used to restore this to serial data. This eliminates the need for FIFO elements that need to secure sufficient capacity, memory circuits that require address control, etc., and simplifies the configuration to enable low-cost system configuration, and also provides highly reliable data rate conversion and phase absorption. Can be

[0050]

As described above in detail, according to the present invention, speed conversion and phase absorption can be performed without using a large-capacity memory, so that an inexpensive and highly reliable system can be obtained. It is possible to provide a phase absorption device including a speed conversion function capable of performing the above.

[Brief description of drawings]

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention.

FIG. 2 is a timing chart on the input side for explaining the operation of FIG.

FIG. 3 is a timing chart on the output side for explaining the operation of FIG.

[Explanation of symbols]

1 ... Input shift register, 2, 3 ... Latch, 4 ... Selector, 5 ... Output shift register, 6 ... Latch timing generation circuit, 7 ... Shift register load timing generation circuit, 8 ... Selector control circuit, 8A ... synchronous phase detector, 8B ... selector switching signal generator, 10 ... input (serial) data, 11 ... input side clock signal, 1
2 ... Input side frame synchronization signal, 13 ... Output (serial) data, 14 ... Output side clock signal, 15 ... Output frame.

Claims (4)

[Claims] 1. A phase absorption device for taking in serially transmitted input data in a frame structure and matching the phase of a transmission frame on the output side and outputting the same to the output side. Parallel data conversion means for converting the input data into parallel data. A first latch means for holding and outputting the parallel data converted by the parallel data converting means at a predetermined timing in accordance with a frame of the input data; and a data held by the first latch means, Hold the data at the timing within the frame period of the input data from the holding timing of the first latch means, and at a timing delayed by a predetermined time corresponding to the holding data of the first latch means being in a stable state. Second latch means for outputting, selecting means for extracting output data of one of the latch means, Serial data conversion means for fetching the output data extracted by the above at a predetermined timing that matches the frame timing on the output side, converting it into serial data, and outputting in synchronization with the transmission timing on the output side; And a control means for designating an extraction target of the selection means according to a phase difference between the latch timing of the latch means and the fetch timing of the serial data conversion means. 2. The phase absorption according to claim 1, wherein the control means is configured to control the selection means so as to extract the output of the first latch means when the phase difference is sufficient. apparatus. 3. The phase absorber according to claim 1, wherein the control means is configured to control the selection means so as to extract the output of the latch means having a sufficient phase difference. 4. The data holding timing of the second latch means is set to be about half a frame cycle of the input data from the data holding timing of the first latch means. The phase absorption device according to claim 1.