JPH01204169A - Bus transfer control system - Google Patents

Abstract

PURPOSE:To realize an inexpensive and highly efficient bus transfer control system by switching a synchronizing clock for transmission of a bus request of a bus master to a system clock or a division clock in accordance with a bus slave of the transmitting destination. CONSTITUTION:A clock switching means 14 switches a synchronizing clock for transmission of signals to a bus request transmission means 5 and an address data transmission means 6 to a system clock or a division clock in accordance with the bus request transmitting destination slaves 4a and 4b. Then a bus request is transmitted to the slave 4b requiring no high-speed process synchronously with the division clock. Thus a busy signal is received in response to the preceding bus request before transmission of the next bus request. Therefore the continuous bus requests are not transmitted and a buffer of a single stage suffices. In such a way, an inexpensive bus transfer control system is obtained.

Description

[Detailed Description of the Invention] [Industrial Application Fields] This invention controls the transfer of data between a bus master such as a CPU or DMA control device and a bus slave such as a storage device or input/output device using a synchronous bus. This invention relates to a bus transfer control method.

[Prior Art] FIG. 3 is a schematic configuration diagram showing a conventional bus transfer control system, and FIG. 4 is a time chart showing signals transferred by a bus. In the figure, (1) is a bus that transfers signals in synchronization with a system clock signal (hereinafter simply referred to as a clock);
(2) is a clock generation means that generates a clock for synchronization, (3) is a bus master such as a CPU that controls transfer by bus (1), (4) is a bus slave such as a storage device or input/output device, and (5) is a bus slave such as a storage device or input/output device. ) is a bus request sending means for sending out a bus request signal (hereinafter simply referred to as a bus request) in synchronization with a clock in order to monopolize the bus (1) between the bus master (3) and a predetermined bus slave (4). , (6) is an address/data sending means that sends out an address signal (hereinafter simply referred to as an address) and a data signal (hereinafter simply referred to as data) in synchronization with a clock at the same time as a bus request, and (7) is a bus slave (4). The bus request sending means (5) receives a busy signal (hereinafter simply referred to as busy) from the
), (8) is a bus request receiving means for receiving a bus request from the bus master (3) in the bus slave (4), (9) is bus request receiving means for stopping the transmission of a bus request synchronized with the next clock from Busy sending means (10) sends out a busy signal in synchronization with a clock in response to reception of a bus request by this means (8); address/data receiving means (10) receives address/data from the bus master (3);
11>, (12) is a buffer memory (hereinafter simply referred to as a buffer) that temporarily stores received address data.
It is.

Next, a signal transfer operation in this bus transfer control method will be explained. Bus (1) has clock generation means (2)
The clock shown in FIG. 4 is sent from the bus master (3) and the bus slave (4) connected to the clock for synchronization. Now, bus master (3
), it is assumed that three signal transfer requests occur successively. First, in response to the first signal transfer request, a bus request RQI is sent from the bus request sending means (5) to the bus (1) in synchronization with the clock.
) is sent. At the same time, address/data sending means (
From 6), the address ADI of the destination bus slave (4) or this and data (not shown) is sent to the bus (1) in synchronization with the clock (hereinafter, only address transfer will be explained for simplicity). . In the destination bus slave (4), the bus request receiving means (8) receives this bus request RQI, and the address/data receiving means (10) receives the address ADI, and the address ADI is stored in the buffer 1 (11). be done. In response to the reception of the bus request RQI, the busy sending means (9) sends out the busy BZI in synchronization with the next clock. This busy BZI is received by the busy receiving means (7) of the bus master (3) and the sending of bus requests in the next clock cycle is stopped. However, in the clock cycle in which the busy BZI is received, the transmission of bus requests is not stopped, so the second bus request RQ2 is transmitted from the bus request transmission means (5) together with the address AD2, and the transfer destination of this is the same bus. If it is the slave (4), these will be received in the same way as described above. However, in this clock cycle, the busy BZI is being sent, so the busy sending means (9
) is driven again and busy BZ2 is not sent out in the next clock cycle, and the received address A
D2 is stored in buffer 2 (12). Busy BZ
No bus request is sent in the next clock cycle after I is sent, and the third bus request RQ3 is sent in the next clock cycle.

In this way, if multiple signal transfer requests occur simultaneously or during the same clock cycle, the bus master (3) will send the bus request, address, or data to it continuously over two clock cycles. Bus slave (4
), it is necessary to provide at least two stages of buffers.

[Problems to be Solved by the Invention] Since the conventional bus transfer control method is performed as described above, it poses a problem for bus slaves that require high-speed processing such as storage devices that perform read/write control. However, there is a problem in that it is necessary to provide two or more stages of buffers even for a bus slave that does not require such high-speed processing, such as a human blade device, which makes the entire device expensive.

This invention was made to solve the above-mentioned problems; it maintains high-speed processing performance for bus slaves that require high-speed processing, and maintains high-speed processing performance for bus slaves that do not require high-speed processing. The purpose of this invention is to obtain a bus transfer control method that can be configured at low cost by simplifying the hardware.

[Means for Solving the Problems] A bus transfer control method according to the present invention generates a frequency-divided clock obtained by dividing a system clock in a synchronous bus, and transfers the synchronous clock for sending a bus request at a bus master to a frequency-divided clock at a destination. The clock can be switched to either the system clock or the divided clock depending on the bus slave.

[Function] The bus transfer control method according to the present invention sends a bus request to a bus slave that does not require high-speed processing in synchronization with a divided clock, so the bus transfer control method according to the present invention sends out a bus request in synchronization with a divided clock, so that the bus transfer control method sends out a bus request in synchronization with a divided clock. bus requests are received, and no consecutive bus requests are sent out, so the buffer is filled with 1
Only steps are required.

[Example] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic configuration diagram showing an embodiment of the present invention, and FIG. 2 is a time chart showing signals transferred thereby. In the figure, (1) is a bus, (2) is a clock generation unit that generates a system clock, (3) is a bus master, (4a) is a bus slave that requires high-speed processing such as a storage device, and (4b) is an input device. A bus slave that does not require high-speed processing such as an output device, (5) is a bus request sending means, (6
) is an address/data sending means, (7) is a busy receiving means, (8a) and (8b) are bus request receiving means, and (9) is a busy receiving means.
a), (9b) is a busy sending means, (10a).

(10b) is address/data receiving means, (lla)
, (12a).

(llb) is a buffer, (13) is a divider by 2 that divides the frequency of the system clock by 172 and sends the divided clock with a period twice the length of the system clock to bus (1), and (14) is Bus request sending means (5) and address/data sending means (6) depending on the slave to which the bus request is sent.
This clock switching means switches the synchronization clock for signal transmission to the system clock and the frequency-divided clock.

Next, the signal transfer operation in this embodiment will be explained. A system clock and a divided clock shown in FIG. 2 are sent to the bus (1) from a clock generating means (2) and a frequency divider (13). Now, assume that two signal transfer requests to a bus slave (4b), such as an input/output device that does not require high-speed processing, occur in succession in the bus master (3). Clock switching means (14) according to this transfer destination
is switched to select the divided clock. First, in response to the first signal transfer request, the bus request RQI is sent from the bus request sending means (5) to the bus (1
) is sent. At the same time, address/data sending means (
6) to the address ADI of the destination bus slave (4b)
is sent to bus (1) in synchronization with the frequency-divided clock. The destination bus slave (4b) receives a bus request receiving means (8).
According to b), the bus request RQI and the address ADI are received by the address/data receiving means (10b), and the address ADI is stored in the buffer (llb). In response to the reception of the bus request RQI, the busy sending means (9b) sends out a busy BZI in synchronization with the next system clock. This busy BZI is received by the busy receiving means (7) of the bus master (3) and the sending of bus requests in the next divided clock cycle is stopped. The second bus request RQ2 and address AD2 are sent out after the lapse of the divided clock cycle in which the sending is stopped.

Bus slaves (4a) that require high-speed processing such as storage devices
), the clock switching means (1
4) is switched to select the system clock, and the subsequent operation is exactly the same as the conventional example explained in FIGS. 3 and 4, so a detailed explanation will be omitted.

In this way, bus slaves (4b) that do not require high-speed processing
) bus requests and address data are sent out in synchronization with the divided clock, and busy signals are sent back in synchronization with the system clock, so although it takes time to transfer the signal, it always occurs before the next bus request is sent. Busy is received in a clock cycle and no subsequent bus requests are issued.

Therefore, it is a bus slave (4b) that does not require high-speed processing.
Only one stage of buffer (11b) is provided.

In addition, in the above embodiment, an example was shown in which a 2-divided clock was used as the synchronization clock for sending bus requests, but in addition to this, 4 clocks were used.
A divided clock may also be provided, and the three clocks including the system clock may be switched depending on the destination bus slave.

Furthermore, three logic devices can issue signal transfer requests to the same bus slave that requires high-speed processing, and in response to a signal transfer request from the first logic device, the second In response to a signal transfer request from the third logic device, a bus request is sent only when the frequency-divided clock is at H level, and in response to a signal transfer request from the third logic device, a bus request is sent only when the frequency-divided clock is at H level. It is also possible to perform contention control between logical devices in this way.

[Effects of the Invention] As described above, according to the present invention, a frequency-divided clock obtained by dividing the system clock is generated in a synchronous bus, and a synchronous clock for sending a bus request in a bus master is transmitted to a bus slave as a destination. Since it is possible to switch to either the system clock or the divided clock depending on the situation, bus slaves that require high-speed transfer can perform high-speed transfer as before, and bus slaves that do not require high-speed transfer can In this case, only one buffer is required, and an overall inexpensive and efficient system can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a schematic configuration diagram showing an embodiment of the present invention, FIG. 2 is a time chart showing signals transferred thereby,
FIG. 3 is a schematic configuration diagram showing a conventional bus transfer control system, and FIG. 4 is a time chart showing signals transferred by the bus. In the figure, (1) is a bus, (2) is a clock generation means, (3) is a bus master, (4a) is a bus slave that requires high-speed processing, (4b) is a bus slave that does not require high-speed processing, ( 5) is a bus request sending means, (6) is an address/data sending means, (7) is a busy receiving means, and (8) is a bus request sending means.
a), (8b) are bus request receiving means, (9a),
(9b) is a busy sending means, (10a), (10
b) is an address/data receiving means, (lla), (
12a) and (llb) are buffers, (13) is a frequency divider by 2, and (14) is a clock switching means. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] A synchronous bus synchronized with the system clock transfers bus requests from the bus master to the bus slave, transfers a busy signal from the bus slave to the bus master in response to the reception of the bus request, and the bus master responds to the reception of this busy signal. In a bus transfer control method in which the sending of a bus request synchronized with the next clock is stopped by a clock, a divided clock obtained by dividing the system clock is generated in the synchronous bus, and the synchronization for sending the bus request in the bus master is A bus transfer control system characterized in that the clock can be switched to either the system clock or the divided clock according to the destination bus slave.