JPS62204359A - Synchronizing data transfer system - Google Patents

Synchronizing data transfer system

Info

Publication number
JPS62204359A
JPS62204359A JP61046645A JP4664586A JPS62204359A JP S62204359 A JPS62204359 A JP S62204359A JP 61046645 A JP61046645 A JP 61046645A JP 4664586 A JP4664586 A JP 4664586A JP S62204359 A JPS62204359 A JP S62204359A
Authority
JP
Japan
Prior art keywords
transfer
data
delay time
register
increase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61046645A
Inventor
Hiroyuki Izumisawa
Original Assignee
Nec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corp filed Critical Nec Corp
Priority to JP61046645A priority Critical patent/JPS62204359A/en
Publication of JPS62204359A publication Critical patent/JPS62204359A/en
Application status is Pending legal-status Critical

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4217Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with synchronous protocol

Abstract

PURPOSE:To avoid the increase of the transfer quantity of data as well as the loss of data in a clock stop mode by using an adjusting means for transfer delay time that increase the transfer delay time more than the transfer cycle time and a data holding buffer that holds data which are under transfer in a clock stop mode. CONSTITUTION:In a synchronizing data transfer mode the data are transferred to the reception register 30 of a logic unit 3 from the transmission register 20 of a logic unit 2 of a data processing system consisting of both logic units 2 and 3 that share a lock unit 1. In such a case, both the maximum and minimum values of the transfer delay time needed for the transfer of data between a transmission register 20 and the register 30 are adjusted so that the transfer delay time is larger than the transfer cycle time. Then the data under transfer are never lost and held by a data holding buffer 40 even though the system clock 1 is stopped in a state where >=2 pieces of transfer data exist on a transfer line at a certain time point. Thus it is possible to increase the transfer quantity of data without increasing the hardware quantity and also to prevent the loss of data in a clock stop mode.
JP61046645A 1986-03-04 1986-03-04 Synchronizing data transfer system Pending JPS62204359A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61046645A JPS62204359A (en) 1986-03-04 1986-03-04 Synchronizing data transfer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61046645A JPS62204359A (en) 1986-03-04 1986-03-04 Synchronizing data transfer system

Publications (1)

Publication Number Publication Date
JPS62204359A true JPS62204359A (en) 1987-09-09

Family

ID=12753047

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61046645A Pending JPS62204359A (en) 1986-03-04 1986-03-04 Synchronizing data transfer system

Country Status (1)

Country Link
JP (1) JPS62204359A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5737589A (en) * 1993-09-20 1998-04-07 Hitachi, Ltd. Data transfer system and method including tuning of a sampling clock used for latching data
US6163464A (en) * 1997-08-08 2000-12-19 Hitachi, Ltd. Apparatus for interconnecting logic boards

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5737589A (en) * 1993-09-20 1998-04-07 Hitachi, Ltd. Data transfer system and method including tuning of a sampling clock used for latching data
US5870594A (en) * 1993-09-20 1999-02-09 Hitachi, Ltd. Data transfer system and method
US6163464A (en) * 1997-08-08 2000-12-19 Hitachi, Ltd. Apparatus for interconnecting logic boards
US6335867B1 (en) 1997-08-08 2002-01-01 Hitachi, Ltd. Apparatus for interconnecting logic boards

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