JPS62204359A - Synchronizing data transfer system - Google Patents

Abstract

PURPOSE:To avoid the increase of the transfer quantity of data as well as the loss of data in a clock stop mode by using an adjusting means for transfer delay time that increase the transfer delay time more than the transfer cycle time and a data holding buffer that holds data which are under transfer in a clock stop mode. CONSTITUTION:In a synchronizing data transfer mode the data are transferred to the reception register 30 of a logic unit 3 from the transmission register 20 of a logic unit 2 of a data processing system consisting of both logic units 2 and 3 that share a lock unit 1. In such a case, both the maximum and minimum values of the transfer delay time needed for the transfer of data between a transmission register 20 and the register 30 are adjusted so that the transfer delay time is larger than the transfer cycle time. Then the data under transfer are never lost and held by a data holding buffer 40 even though the system clock 1 is stopped in a state where >=2 pieces of transfer data exist on a transfer line at a certain time point. Thus it is possible to increase the transfer quantity of data without increasing the hardware quantity and also to prevent the loss of data in a clock stop mode.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a synchronous data transfer system, and more particularly to a synchronous data transfer system between logical units that share a clock source in a data processing system.

[Conventional technology]

Conventionally, in this type of synchronous data transfer method between logical units, the transfer cycle time is limited by the delay time required for data transfer between the transmit register and the receive register, and the transfer cycle time is set smaller than the transfer delay time. could not.

[Problem that the invention seeks to solve]

In the conventional synchronous data transfer method described above, as the clock speed of a data processing device becomes faster, the physical distance between logical units that operate synchronously becomes a problem. If the transfer delay time between logical units becomes relatively large compared to the clock and cannot be accommodated within one clock time, the transfer cycle must be set to two or more clocks.

In this case, in order to maintain the conventional transfer amount in one clock cycle, it is necessary to more than double the data transfer width, which has the drawback of increasing the amount of hardware.

Furthermore, if the transfer cycle is kept at one clock in a state where the transfer delay time exceeds one clock time, two or more pieces of transfer data will exist on the transfer line at one point in time. The disadvantage is that if the system clock stops, data that is being transferred is lost.

In view of the above points, an object of the present invention is to provide a synchronous data transfer method that can increase the amount of transfer without increasing the amount of hardware and can prevent data loss when the clock stops. .

[Means for solving problems]

The synchronous data transfer method of the present invention is a synchronous data transfer method in which data is transferred from the transmission register of one logical unit to the reception register of another logical unit in a data processing system consisting of a plurality of logical units that share a clock source. , a transfer delay time adjusting means for adjusting a maximum value and a minimum value of a transfer delay time required for data transfer between the transmitting register and the receiving register, and making the transfer delay time longer than the transfer cycle time; The data holding buffer 7 is provided between the register and the receiving register and holds data that is being transferred when the clock is stopped.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of a data processing system to which a synchronous data transfer method according to an embodiment of the present invention is applied. This data processing system includes a clock unit 1 and a plurality of logical units 2 and 3 (only two are shown in the figure).
Its main parts are composed of:

The clock unit l is a clock oscillator (O3C) 10
．． It is configured to include a clock distributor 11 and a clock control section 12.

The logic unit 2 is configured to include a transmission register 20 and a clock distributor 21.

The logic unit 3 includes a reception register 30, a clock distributor 31, a data holding buffer 40, and a delay circuit 41.

The transmission register 20 of the logic unit 2 and the reception register 30 of the logic unit 3 are connected via a wire 4. This wire 4 is expressed in a notation representing a delay element to emphasize that it has a delay time αt.

Transmission register 20, reception register 30 and data holding buffer 40 are supplied with the same clock via clock distributors 11, 21 and 31 using clock oscillator 10 as a common clock source. However, the data holding buffer 40 receives a clock from the clock distributor 31 via a delay circuit 41 with a delay of one clock time.

The period of the clock is T, the clock skew between the transmitting register 20 and the receiving register 30 is Ts, and the length of the wire 4 is 1 m.
Let the hit delay time be tw (1±δ), where:
δ indicates variation due to material, environment, etc. The output time of the transmitting register 20 is assumed to be TF, the set-up time of the receiving register 30 is assumed to be T, and the hold time is assumed to be TlIn.

As shown in FIG. 2, transfer data D+, Dt, Ds, . . . are sequentially sent to the transmission register 20 every clock. The output of the transmitting register 20 is sent to the receiving register 3.
Based on the 0 clock, TF±T.

When the length of the wire 4 with a delay time of
When shown with x and 1lin, Twin −Ty
sin −Ts +L−t@(1−δ)≧T, +TN1
1...+11'r++ax -TF
raax +T1 +L-tw (1+δ)ku2・T
c-Ts++ (2), as shown in FIG. 2, the data D+ sent to the transmission register 20 at clock 1 is received by the reception register 30 two clocks later.

For example, Tc-8ns, Ts-1nss t, =4
ns/m, δ=0.1% TF min =Ons,
T.

max −1n s, Tl (1−TMl= 1 n
If s is the formula % formula % From formula (2), L < - < 2.95 m 4X1.1, so the wire length of the wire 4 is 2.77 m or 2.95 m.
It turns out that all you have to do is choose m.

The case where the transfer time is 2 clocks and the transfer cycle is 1 clock has been described above, but if the variation δ of the wire 4 and the clock skew T are set small, the degree of freedom in selecting the number of clocks will be greater.For example, Setting the transfer time to 3 clocks and the transfer cycle to 2 clocks, formula (11)
, Equation (2) becomes Equation (3) and Equation (4), respectively.

Twin −Ty sin −Ts +L
-t+n (1-6)≧2・Tc+T, In
...(3) Tmax = Ty IIax + Ts
+L-tw (1+δ)<3-Te-'rst+
...(4) In general, the transfer time is 2 clocks, the transfer cycle is m (<j clocks, 'rgin -Ty win -T, +L-tw
(L-δ)≧m-Tc+T,,,,...
(5) T+*ax =Tyl1ax +T* +L-
t@(1+δ)<1-T(Tsu...
(6) Any number of clocks can be selected within the range that satisfies the constraints of equations (5) and (6).

Next, the role of the data holding buffer 40 will be explained with reference to FIGS. 1 and 3. FIG. 3 is a time chart of data transfer when the clock is stopped. The clock is started and stopped according to instructions from the clock control section 12. 'Referring to FIG. 3, normally, the receiving register 30 and the data holding buffer 40 simultaneously receive the data sent from the transmitting register 20 after two clocks have elapsed, such as clocks 1, 2, or 3.4. Receive. If the clock is stopped after clock 2 is generated, the receiving register 30 cannot receive data DI. Since the data in the transmission register 20 has already changed to data D2 at this point, the data D1 being transferred is received by the data holding buffer 40 in synchronization with the delay clock 2' from the delay circuit 41. During the clock stop period, the control signal 5 from the clock control unit 12 becomes "1",
As a result, the input of the receiving register 30 is switched to the data holding buffer 40. When the clock is restarted and clock 3 is generated, data D in the data holding buffer 40 is set in the receiving register 30. Immediately after this, the control signal 5 returns to 0°, the input of the reception register 30 is switched to the transmission register 20 side, and the data D2 on the transfer path is received by the reception register 30 at clock 4.

〔Effect of the invention〕

As explained above, the present invention transfers data between synchronized transmitting registers and receiving registers in transfer cycles with fewer clocks than the number of clocks required for the transfer time, thereby reducing the amount of data transferred without increasing the amount of hardware. This has the effect that it is possible to increase the amount of data, and to prevent data loss at the time of stoppage.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a time chart for explaining the relationship between transfer delay time and transfer cycle time in the synchronous data transfer method shown in FIG. FIG. 3 is a time chart for explaining the operation when the clock is temporarily stopped in the synchronous data transfer method shown in FIG. In the figure, 1... clock unit, 2.3... logic unit, 4... wire, 10... clock oscillator, 11, 21.3 clock distributor, 12. ... Clock control section, 20 ... Transmission register, 30 ... Reception register, 40 ... Data holding buffer, 41 ... Delay circuit.

Claims (1)

[Scope of Claims] In a synchronous data transfer method in which data is transferred from a transmission register of one logical unit to a reception register of another logical unit in a data processing system consisting of a plurality of logical units that share a clock source, the transmission register comprises: transfer delay time adjusting means for adjusting a maximum value and a minimum value of a transfer delay time required for data transfer between the data transfer register and the receiving register, and making the transfer delay time larger than the transfer cycle time; and the transmitting register and the receiving register. 1. A synchronous data transfer method comprising: a data holding buffer provided between the clock and the data holding buffer for holding data in the middle of transfer when a clock is stopped.