JPH0263000B2 - - Google Patents

Description

[Detailed description of the invention] 〔Technical field〕 The present invention relates to time division call signaling.

[Prior art]

Conventionally, in time-division electronic exchanges, clock signals and time-division call signals are transferred to a duplex time-division system in order to avoid system failure when an abnormality occurs in the clock signal and time-division call signal used within the system. A communication path circuit configuration is adopted in which communications are sent and received over a communication path. However, as shown in FIG. 1, in the conventional example, even if the clock signals are synchronized between the clock sources 106 and 109 of the time division switches 104 and 107,
Due to the difference in the transmission path of the clock signals to the input to the clock signal selection circuit 101 in the time division speech signal receiving circuit 100, a phase difference occurs between the clock signals. There is a phase difference between the selected output of the clock signal selection circuit 101 and the serial time-division call signal output from the first time-division signal transmission circuit 105 or the serial time-division call signal output from the second time-division signal transmission circuit 108. There is a first synchronous circuit 102
Since there is little time margin required for synchronization due to this phase difference in either of the synchronous circuits 102 and 103, the time division call signal is received at the output of the first synchronous circuit 102 or the second synchronous circuit 103. An error occurs, resulting in an error signal being communicated to time division call signal processing circuit 110.

[Purpose of the invention]

An object of the present invention is to input a duplexed clock signal and serial time-division communication signals synchronized with each other to a time-division signal receiving circuit of a duplex time-division communication path circuit, perform parallel conversion or low-speed conversion, By synchronizing with the clock signal of
An object of the present invention is to provide a time-division call signal system capable of preventing reception errors of time-division call signals.

[Summary of the invention]

The time-division communication signal system according to the present invention has a duplex time-division communication path, and signals are transmitted from a first time-division communication path and a second time-division communication path that operate with clock signals of the same synchronization but different phases. A serial time-division call signal is converted into a parallel signal in a time-division call signal receiving circuit using a clock signal received from each of the communication paths to reduce the speed, and this low-speed parallel time-division call signal is used as a clock signal within the system. It is characterized by synchronous reception using signals.

[Explanation of Examples]

Next, embodiments of the present invention will be described with reference to the drawings.

Referring to FIG. 2, in one embodiment of the present invention, a first clock source 202 comprising a first time division switch 200 is connected to a first time division path 200.
3 to one input of the clock selection circuit 209 of the time division speech signal receiving circuit 208 and the clock input of the first parallel low speed conversion circuit 210. Further, the first time-division call signal transmission circuit 2
The output of 01 is the first parallel low speed conversion circuit 21
Connected to data input 0. On the other hand, the second clock source 206 constituting the second time division switch 204 is connected to the other input of the clock selection circuit 209 of the time division speech signal receiving circuit 208 via the second time division communication path 207. It is connected to the clock input of the parallel low speed conversion circuit 212. Further, the output of the second time-division call signal transmission circuit 205 is connected to the data input of the second parallel low-speed conversion circuit 212. Further, the clock output of the clock selection circuit 209 is transmitted to the first synchronization circuit 211.
, a clock input of a second synchronization circuit 213, and a clock input of a time division speech signal processing circuit 214, respectively. A data output of the first parallel low-speed conversion circuit 210 is connected to a data input of a first synchronization circuit 211, and a data output of the first synchronization circuit 211 is connected to an input of a time-sharing speech signal processing circuit 214. . The data output of the second parallel low-speed conversion circuit 212 is connected to the data input of the second synchronization circuit 213,
The data output of the synchronization circuit 213 is connected to the input of the time division speech signal processing circuit 214.

Here, the first time division switch 200 and the second
Even when the first and second clock signals output from the time division switch 204 are synchronized with each other, they pass through the first time division communication path 203 and the second time division communication path 207, respectively, and the clock signals are output from the time division switch 204. When reaching the selection circuit 209, the third
A phase difference occurs as shown in the figure. Even if the clock selection circuit 209 operates so that the first clock signal output from the first time division switch 200 is the third clock signal used in the system, the first time division communication path 203 and The first parallel low speed conversion circuit 210 uses the first and second clock signals synchronized with the time division communication signal output from the second time division communication path 207, respectively.
Then, if the second parallel low speed conversion circuit 212 performs parallel low speed conversion as shown in FIG.
And the second synchronization circuits 211, 213, 122 can be synchronized with the first clock signal. That is, when the time-division call signal input to the time-division call signal receiving circuit 208 is synchronized with the third clock signal selected by the system, the time-division call signal synchronized with the non-selected clock signal cannot be received. However, as mentioned above, the first and second
According to the configuration in which one of the clock signals is selected and used as the third clock signal, it is possible to reliably receive the signal obtained by parallel low-speed conversion using the clock signal with which the time-division call signal is synchronized, using the selected clock signal, and It is possible to compensate for the clock phase difference caused by duplicating the communication path and realize a stable time-division communication path circuit.

〔Effect of the invention〕

As explained above, according to the present invention, the duplexed clock signal and the serial time-division call signal synchronized with each other are converted to parallel low speed using the synchronizing clock signal, and synchronization is achieved using one of the selected clock signals. As a result, time-division call signals can be received without error.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a conventional time-division channel circuit, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is an explanatory diagram of the operation of the same embodiment. 200, 204...Time division switch, 201,
205...Time division call signal transmission circuit, 202,2
06...Clock source, 203, 207...Time division communication unit, 208...Time division communication signal receiving circuit, 2
09...Clock selection circuit, 210, 212...
Parallel low speed conversion circuit, 211, 213...Synchronization circuit, 214...Time division call signal processing circuit.

Claims (1)

[Claims] 1. In a time-division electronic exchange having a duplex configuration of time-division communication paths, the first and second time-division communication paths of the duplex configuration operate with first and second clock signals having mutually different phases, and The serial time-division call signals respectively transmitted on the second time-division call path are converted into parallel low-speed signals using the first and second clock signals, and the parallel low-speed converted time-division call signals are converted into the first and second time-division call signals.
and a second clock signal for phase synchronization.