JPS6328147A - Synchronizing system in optical intermediate repeater - Google Patents
Synchronizing system in optical intermediate repeaterInfo
- Publication number
- JPS6328147A JPS6328147A JP61173122A JP17312286A JPS6328147A JP S6328147 A JPS6328147 A JP S6328147A JP 61173122 A JP61173122 A JP 61173122A JP 17312286 A JP17312286 A JP 17312286A JP S6328147 A JPS6328147 A JP S6328147A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- synchronization
- circuits
- branching
- subsystem
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003287 optical effect Effects 0.000 title claims abstract description 14
- 230000005540 biological transmission Effects 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims description 3
- 230000001360 synchronised effect Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000013307 optical fiber Substances 0.000 description 2
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
Landscapes
- Time-Division Multiplex Systems (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は光ファイバによる高速ディジタル伝送システム
に関し、特に中間中継装置に使用される簡易化した同期
化回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high-speed digital transmission system using optical fiber, and particularly to a simplified synchronization circuit used in an intermediate repeater.
従来、この種の高速ディジタル伝送システムの中間中継
装置では、主信号の中から補助データ信号を分岐したシ
逆に挿入したシする場合、同期化回路で７レ一ム同期を
とシ、補助データのビットの信号を分岐・挿入している
。Conventionally, in the intermediate repeater of this type of high-speed digital transmission system, when an auxiliary data signal is branched from the main signal and inserted in the opposite direction, a synchronization circuit performs 7-rem synchronization, and the auxiliary data signal is The bit signals are branched and inserted.
上述した従来の中間中継装置における同期化方式は、中
間中継装置１台につき、伝送するシステム数と同一数の
同期化回路が必要となシ、補助データ信号の分岐・挿入
が常時性なわれ゛る必要が無い様なシステム、例えば、
中間中継装置でのエラーレイト等のアラーム情報やステ
ータス情報を間欠的に端局側へ送信すれば良いシステム
においても尋問期化回路の規模は増大し、主信号の伝送
速度が大きい程、実装スペースや消費電力がより大きく
なるという欠点がある。The synchronization method in the conventional intermediate relay device described above requires the same number of synchronization circuits as the number of systems to be transmitted for each intermediate relay device, and the branching and insertion of auxiliary data signals is constant. For example, a system that does not require
Even in systems that only need to intermittently transmit alarm information such as error rates and status information from intermediate repeaters to the terminal side, the scale of the interrogation circuit increases, and the larger the transmission speed of the main signal, the more mounting space is required. The disadvantage is that the power consumption is higher.
本発明の中間中継装置に使用される同期化回路の構成は
、中間中継装置内のシステム（ポート）数が複数の場合
、常時受信信号の同期をとっているシステムは一つのシ
ステムとして（以下メインムからの制御によシ必要に応
じて同期化回路に接続されることによって補助データ信
号の分岐・挿入を行なう機能を有している。The configuration of the synchronization circuit used in the intermediate relay device of the present invention is that when there are multiple systems (ports) in the intermediate relay device, the system that constantly synchronizes received signals is treated as one system (hereinafter referred to as the main system). It has the function of branching and inserting auxiliary data signals by being connected to a synchronization circuit as necessary under control from the auxiliary data signal.
次に本発明の実施例について図面を参照して説明する。 Next, embodiments of the present invention will be described with reference to the drawings.
図は本発明の一実施例を示すブロック図である。The figure is a block diagram showing one embodiment of the present invention.
メインシステムの同期化回路２は常時光受信回路１の出
力（電気信号）の同期をとってサブシステムへの切替制
御信号を出している。一方、サブシステムでは光受信回
路１１，２１．３１の出力を分岐回路１２，２２，３２
１ｒ：介して選択回路４１へ出力し、同期化の制御が無
い場合は分岐回路１２，２２．３２の出力が選択回路１
３，２３゜３３を経て光送信回路１４，２４．３４へ供
給される。同期化の制御をメインシステムの同期北回（
路２から受けた場合、サブシステムの出力は、共用の同
期化回路４２により同期がとられ、補助データ信号を分
岐した）工２−パルスのカク／トをしたシした後、補助
データ信号を挿入し、分岐回路４３、及び選択回路１３
または２３または３３を経て、光送信回路１４または２
４またＶｉ３４に送出される。A synchronization circuit 2 of the main system constantly synchronizes the output (electrical signal) of the optical receiver circuit 1 and outputs a switching control signal to the subsystem. On the other hand, in the subsystem, the outputs of the optical receiver circuits 11, 21.31 are sent to the branch circuits 12, 22, 32.
1r: Outputs to the selection circuit 41 via, and if there is no synchronization control, the outputs of the branch circuits 12, 22, and 32 are output to the selection circuit 1.
The signal is supplied to the optical transmission circuits 14, 24, and 34 through the optical fibers 14, 23, and 33. Synchronization control of main system synchronization north (
2, the output of the subsystem is synchronized by a shared synchronization circuit 42, which splits the auxiliary data signal. Insert, branch circuit 43, and selection circuit 13
Or via 23 or 33, the optical transmission circuit 14 or 2
4 is also sent to Vi34.
以上説明したように本発明は、中間中継装置の同期化回
路を、メインシステムからの制御により、他のシステム
においては時間的に共有することによシ、同期化回路の
数を減少させることが可能となシ、主信号の伝送速度が
大きい種間期化回路の実装スペースや消費電力の増大を
抑える効果が大きくなる。As explained above, the present invention makes it possible to reduce the number of synchronization circuits by sharing the synchronization circuits of intermediate relay devices temporally with other systems under control from the main system. If this is possible, the effect of suppressing the increase in the mounting space and power consumption of the interspecies periodization circuit, which has a high transmission speed of the main signal, can be increased.
図は本発明の一実施例を示すブロック図である。
１・・・−・・メインシステム光受信回路、２・・・・
・・メインシステム同期化回路、３・・・・・・メイン
システム光送信回路、１１，２１．３１・・・・・・サ
ブシステム光受信回路、１２，２２．３２・・・・・・
サブシステム分岐回路、１３，２３．３３・・・・・・
サブシステム選択回路、１４，２４．３４・・・・−・
サブシステム光送信回路、４１・゛・°°・選択回路、
４２・・・・・・共用同期化回路、４３・・−・・・分
岐回路。The figure is a block diagram showing one embodiment of the present invention. 1...- Main system optical receiver circuit, 2...
... Main system synchronization circuit, 3 ... Main system optical transmission circuit, 11, 21.31 ... Subsystem optical reception circuit, 12, 22.32 ...
Subsystem branch circuit, 13, 23. 33...
Subsystem selection circuit, 14, 24.34...
Subsystem optical transmission circuit, 41・゛・°°・selection circuit,
42... Shared synchronization circuit, 43... Branch circuit.
Claims (1)
期方式において、伝送信号に補助データ信号の分岐、挿
入を間欠的に行なう場合、前記複数のポートで１つの同
期化回路を共用化することを特徴とする同期方式。In a synchronization method for a high-speed optical intermediate repeater that transmits signals from a plurality of ports, when branching and inserting an auxiliary data signal into a transmission signal is performed intermittently, one synchronization circuit is shared by the plurality of ports. A synchronization method characterized by
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61173122A JPS6328147A (en) | 1986-07-22 | 1986-07-22 | Synchronizing system in optical intermediate repeater |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61173122A JPS6328147A (en) | 1986-07-22 | 1986-07-22 | Synchronizing system in optical intermediate repeater |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6328147A true JPS6328147A (en) | 1988-02-05 |
Family
ID=15954542
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61173122A Pending JPS6328147A (en) | 1986-07-22 | 1986-07-22 | Synchronizing system in optical intermediate repeater |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6328147A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01220923A (en) * | 1988-02-29 | 1989-09-04 | Fujitsu Ltd | Optical signal transmission control system |
| US6096402A (en) * | 1996-01-30 | 2000-08-01 | Hashimoto Forming Industry Co., Ltd. | Elongate composite member having a longitudinally varying cross-sectional shape, as well as method of, and apparatus for manufacturing the same |
-
1986
- 1986-07-22 JP JP61173122A patent/JPS6328147A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01220923A (en) * | 1988-02-29 | 1989-09-04 | Fujitsu Ltd | Optical signal transmission control system |
| US6096402A (en) * | 1996-01-30 | 2000-08-01 | Hashimoto Forming Industry Co., Ltd. | Elongate composite member having a longitudinally varying cross-sectional shape, as well as method of, and apparatus for manufacturing the same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5598442A (en) | Self-timed parallel inter-system data communication channel | |
| KR960009749A (en) | Audio / Video / Data Component System Buses | |
| KR850008074A (en) | Bus Units in Time Division Multiple Systems | |
| EP0156213A2 (en) | Apparatus and method for providing a transparent interface across a satellite communications link | |
| JPS6328147A (en) | Synchronizing system in optical intermediate repeater | |
| KR880700580A (en) | Asynchronous Addressing Multiple Communication System | |
| US6023768A (en) | Phase locked distributed time reference for digital processing and method therefor | |
| WO1980000883A1 (en) | Time multiplex controlled data system | |
| JPH07123247B2 (en) | Digital data transmission method | |
| KR950004509B1 (en) | Bus connecting circuit in long distance interface units | |
| TW347621B (en) | Method and arrangement for increasing data transmisssion rate over telephone cable | |
| JPH02119347A (en) | Loop type data transmission system | |
| JP3230308B2 (en) | Ring LAN | |
| JPS63290031A (en) | Monitor system for light intermediate repeating device | |
| JPS6223651A (en) | Data transmission equipment | |
| JPS6341456B2 (en) | ||
| JPH0129466B2 (en) | ||
| JPS6292534A (en) | Pcm intermediate repeater | |
| JPH1174856A (en) | Data transfer system | |
| JPH02285822A (en) | Time division multiple access system satellite communication system | |
| JPH0117625B2 (en) | ||
| JPS62224141A (en) | Data transmission system | |
| JPH0344140A (en) | Control system for self-routing switch | |
| EP0950336A2 (en) | Method and apparatus to interconnect two or more cross-connects into a single pcm network | |
| JPH0314258B2 (en) |