JPH0282834A - Loop back control system - Google Patents
Loop back control systemInfo
- Publication number
- JPH0282834A JPH0282834A JP63233684A JP23368488A JPH0282834A JP H0282834 A JPH0282834 A JP H0282834A JP 63233684 A JP63233684 A JP 63233684A JP 23368488 A JP23368488 A JP 23368488A JP H0282834 A JPH0282834 A JP H0282834A
- Authority
- JP
- Japan
- Prior art keywords
- loop back
- station equipment
- circuit
- slave station
- clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 claims description 11
- 230000005540 biological transmission Effects 0.000 abstract description 10
- 238000004891 communication Methods 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000001419 dependent effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Landscapes
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は折返し制御方式に係シ、特に従属同期網に適用
される装置の対向装置側への折返し制御方式に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a loopback control method, and more particularly to a loopback control method for a device applied to a slave synchronous network to an opposite device side.
従来の折返し制御方式の一例を第2図に示し説明する。 An example of a conventional foldback control method is shown in FIG. 2 and will be described.
従来、この種の折返し制御方式は対向装置からの信号を
そのまま自装置内で折返す方式であり、第2図に示すよ
うに、主局装置5と従局装置6間の通信において、折返
し回路7−1.7−2は伝送路8−1.8−2を介して
各々折返しを行うものであシ、点線で示す従属クロック
の流れを構成するものとなってい丸。Conventionally, this type of loopback control method is a method in which a signal from an opposite device is looped back within its own device, and as shown in FIG. -1.7-2 are looped back via transmission lines 8-1 and 8-2, and constitute the flow of slave clocks shown by dotted lines.
上述した従来の折返し制御方式では、対向装置からの信
号をその11折返す回路となっているので、主局装置が
従局装置へ折返しを行う場合、従属クロックの発生源が
なくなる、すなわち、通常は主局装置のクロック信号を
従属クロックとして従局装置が動作するが、主局装置が
折返しを行うと従局装置は自装置の出力クロックが自装
置の入力クロックとなることとなシ、折返しによる通信
ができなくなるという課題があった。In the conventional loopback control method described above, the circuit loops back the signal from the opposite device, so when the master station loops back the signal to the slave station, the source of the slave clock disappears, that is, normally The slave device operates using the master station device's clock signal as the slave clock, but when the master station device loops back, the slave device's own device's output clock becomes its own device's input clock, and communication due to loopback is not possible. The problem was that it was no longer possible.
本発明の折返し制御方式は、従属同期網で構成される装
置の対向装置側に折返しを行う折返し回路において、そ
の折返し回路にバッファメモリ回路を内蔵し、網内クロ
ックの従属同期を保持するようにしたものである。The loopback control method of the present invention includes a buffer memory circuit built into the loopback circuit that loops back to the opposite device side of a device constituted by a slave synchronization network to maintain slave synchronization of clocks within the network. This is what I did.
本発明においては、対向装置からの信号を単に折返すこ
となくバックアメモリ回路を介し、受信信号を折返しを
しない状態である通常状態と同じ送信りpツクでバッフ
ァリングして送出する。In the present invention, the signal from the opposing device is not simply looped back, but is buffered and sent via the backup memory circuit using the same transmission port as in the normal state where loopback is not performed.
以下、図面に基づき本発明の実施例を詳細に説明する。 Hereinafter, embodiments of the present invention will be described in detail based on the drawings.
第1図は本発明による折返し制御方式の一実施例を示す
構成図である。FIG. 1 is a block diagram showing an embodiment of the loopback control method according to the present invention.
図において、1は主局装置、2は従局装置、3−1.3
−2は折返し回路で、この折返し回路3−1゜3−2に
バッファメモリ回路(図示せず)をそれぞれ内蔵し、網
内クロックの従属同期を保持するように構成されている
。4−1.4−2は伝送路である。In the figure, 1 is the main station device, 2 is the slave station device, 3-1.3
Reference numeral 2 denotes a return circuit, and each of the return circuits 3-1 and 3-2 has a built-in buffer memory circuit (not shown), and is configured to maintain slave synchronization of the clock within the network. 4-1.4-2 is a transmission line.
つぎにこの第1図に示す実施例の動作を説明する。Next, the operation of the embodiment shown in FIG. 1 will be explained.
まず、通常、主局装置1と従局装置2間の通信は伝送路
4−1.4−2を介して行なわれ、折返し回路3−1.
3−2は各々折返し指示時受信信号を対向装置に折返す
構成をとる。図中点線は従属クロックの流れを示す。First, normally, communication between the main station device 1 and the slave station device 2 is carried out via transmission paths 4-1, 4-2, and return circuits 3-1.
3-2 each takes a configuration in which the received signal is returned to the opposing device when a return instruction is given. The dotted line in the figure shows the flow of the dependent clock.
つぎに1従局装置2が折返し指示を受け、折返し回路3
−2を動作させた場合、この折返し回路3−2は受信信
号をバックアメモリに主局装置1からの従属クロックで
書込み、従局装置2の出力クロックで読み出して送信信
号として対向装置へ送出する。Next, the first slave station device 2 receives a loopback instruction, and the loopback circuit 3
-2 is operated, this folding circuit 3-2 writes the received signal into the backup memory using the slave clock from the master station device 1, reads it out using the output clock of the slave station device 2, and sends it as a transmission signal to the opposing device.
また、主局装置1の折返し回路3−1の動作も同様にそ
の指示時、従局装置2からの受信信号を折返し回路3−
1のバックアメモリに書込み、主局装置1の送信クロッ
クで読み出して従局装置2へ折返しを行う。Similarly, the operation of the loopback circuit 3-1 of the master station device 1 is similar to that of the loopback circuit 3-1 when receiving a signal from the slave station device 2.
The data is written in the backup memory of No. 1, read out using the transmission clock of master station device 1, and sent back to slave station device 2.
以上説明したように本発明は、バックアメモリ回路を内
蔵した折返し回路を実現することによシ、主局、従局の
区別なく折返し制御による通信が可能となシ、保守運用
面などにおいてすぐれた機能を発揮し、高信頼のシステ
ムを提供できる効果がある。As explained above, the present invention realizes a loopback circuit with a built-in backup memory circuit, thereby making it possible to communicate by loopback control without distinguishing between master and slave stations, and providing excellent functionality in terms of maintenance and operation. This has the effect of providing a highly reliable system.
第1図は本発明による折返し制御方式の一実施例を示す
構成図、第2図は従来の折返し制御方式の一例を示す構
成図である。
1・拳・・主局装置、2・・・・従局装置、3−1.3
−2・・―−折返し回路、4−1.4−2@・・・伝送
路。
第1図FIG. 1 is a block diagram showing an embodiment of a loopback control method according to the present invention, and FIG. 2 is a block diagram showing an example of a conventional loopback control method. 1. Fist...Main station device, 2...Slave station device, 3-1.3
-2...-Return circuit, 4-1.4-2@...Transmission line. Figure 1
Claims (1)
う折返し回路において、その折返し回路にバッファメモ
リ回路を内蔵し、網内クロックの従属同期を保持するよ
うにしたことを特徴とする折返し制御方式。A loopback control characterized in that, in a loopback circuit that loops back to the opposite device side of a device constituted by a slave synchronization network, a buffer memory circuit is incorporated in the loopback circuit to maintain slave synchronization of clocks within the network. method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63233684A JPH0282834A (en) | 1988-09-20 | 1988-09-20 | Loop back control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63233684A JPH0282834A (en) | 1988-09-20 | 1988-09-20 | Loop back control system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0282834A true JPH0282834A (en) | 1990-03-23 |
Family
ID=16958920
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63233684A Pending JPH0282834A (en) | 1988-09-20 | 1988-09-20 | Loop back control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0282834A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0730358A1 (en) * | 1995-03-01 | 1996-09-04 | Philips Communication D'entreprise | Control system for a transmission chain |
JP2010192452A (en) * | 2010-04-05 | 2010-09-02 | Satori S-Tech Co Ltd | Trigger switch |
-
1988
- 1988-09-20 JP JP63233684A patent/JPH0282834A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0730358A1 (en) * | 1995-03-01 | 1996-09-04 | Philips Communication D'entreprise | Control system for a transmission chain |
FR2731309A1 (en) * | 1995-03-01 | 1996-09-06 | Trt Telecom Radio Electr | CONTROL SYSTEM FOR A TRANSMISSION CHAIN |
JP2010192452A (en) * | 2010-04-05 | 2010-09-02 | Satori S-Tech Co Ltd | Trigger switch |
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