JPH04156022A - Frame phase synchronizing circuit - Google Patents

Abstract

PURPOSE:To obtain satisfactory transmission quality even when synchronizing step-out occurs by duplexing a transmission line, writing reception data on arbitrary dual port memory on which data can be read and written arbitrarily, respectively, reading out the data by a reference clock, and selecting normal data via a selective circuit. CONSTITUTION:The data received by a duplexed transmission line is written on the dual port memory(RAM)5, 6, respectively, and after it is read out by an arbitrary phase, either reception data is selected by the selective circuit 13, however, when the synchronizing step-out occurs in selected reception data, the selective circuit 13 is operated so as to select normal reception data. At this time, since the frame phases of respective reception data read out from the RAMs 5, 6 coincide with each other, the normal data can be always outputted from the selective circuit 13 even when a fault such as the synchronizing step-out, etc., occurs and the selected reception data is switched. Thereby, the transmission quality of output data can be secured.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a frame phase synchronization circuit for a transmission device.

[Conventional technology]

Conventional frame synchronization circuit is a digital communication technology Kimio Tanaka Tokai University Press,! :D3.3.3 As shown in FIGS. 3, 27 and 3, 28 of the synchronous multiplex converter in Chapter D3.3.3, phase synchronization is performed using one ES for one frame.

[Problem to be solved by the invention]

The above-mentioned conventional technology does not take into consideration the quality of data transmission after a forward protection operation when a failure such as out of synchronization occurs in the input data and until the failure such as out of synchronization is confirmed. There may be a problem when transmitting the signal.

An object of the present invention is to provide a transmission device that maintains good transmission quality even when out-of-synchronization occurs.

[Means to solve the problem]

In order to achieve the above object, the present invention duplicates the transmission line, uses a dual port memory (hereinafter abbreviated as RAM) in which data can be written and read, writes received data to each RAM, and uses a reference clock. Data is read out from each RAM using the following steps, and normal data is selected via a selection circuit.

In addition, if a failure such as loss of synchronization occurs in any of the received data, the selection circuit is operated to select the normal received data, and to ensure the transmission quality of the received data, the readout of the RAM is performed. The writing phase difference is set to three frames or more of the received frame.

Furthermore, a frame number identification signal is added to the received data so that the frame phase of the received data can be identified, and the RAM
The readout frames are made to match each other.

[Effect]

Data received through the duplexed transmission lines is written to each dual port memory (hereinafter abbreviated as RAM),
After being read out at an arbitrary phase, the selection circuit selects one of the received data, but if the selected reception data becomes out of synchronization, the selection circuit selects other normal reception data. Since it operates to select, the selection circuit always outputs normal data. At this time, since the frame phases of each received data read from the RAM match,
As mentioned above, even if a failure such as loss of synchronization occurs and the selected received data is switched, normal data will always be output from the selection circuit and the transmission quality of the output data will be ensured. Become.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

Receiving circuits 1 and 2 receive each data from the duplexed transmission path, regenerate the data and clock, detect failures such as loss of synchronization of received data, and output alarm signals. Frame phase detection circuits 3 and 4 detect the frame phase of the received data from the frame number identification signal in the received data, and output a frame phase signal. RAM5.
6, writing and reading are optional. Write address control circuits 7 and 8 generate address signals when writing received data to the RAM. Read address control circuit 9. IO generates an address signal when reading received data from the RAM. The phase comparison circuit 11 compares each frame phase signal from the frame phase detection circuit 3.4 and obtains a reference clock φ. to occur. Alarm control circuit 1
2 determines whether a fault has occurred in the transmission line based on the presence or absence of an alarm signal from the receiving circuit 1.2, and sends a data selection signal to select received data from a normal transmission line where no fault has occurred. Output. The data selection signal 13 is applied to each RA according to the data selection signal from the alarm control circuit 12.
The received data output from M is selected and output.

In Figures 1 and 2, assuming that the duplex transmission path is normal and no failure has occurred, receiving circuits 1 and 2 reproduce the data and clock from the received data and frame the data. Output to phase detection circuits 3 and 4 and write clock to address control circuits 7 and 8
Output to.

Write address control circuits 7 and 8 generate data write addresses for RAMs 5 and 6 based on the clocks from reception circuits 1 and 2, and output them to RAMs 5 and 6.

RAM5 and 6 are write address control circuits 7 and 8
According to the data write address of
Write sequentially.

Frame phase detection circuits 3 and 4 detect the frame phase of the received data from the frame number identification signal in each received data, and output the frame phase signal to the phase comparison circuit 11. The phase comparator circuit 11 compares each frame phase signal from the frame phase detection circuits 3 and 4 and obtains a reference clock φ. to occur. Note that at this time, the reference clock φ. is outputted from the phase comparison circuit at a timing delayed by three frames or more with respect to the phase written in the RAMs 5 and 6.

Read address control circuits 9 and 10 are reference clocks φ from the phase comparator circuit 11. Accordingly, data read addresses for RAM5 and 6 are generated, and data read addresses for RAM5 and 6 are generated.
Output to. RAMs 5 and 6 follow data read addresses from read address control circuits 9 and 10,
Output the written received data. At this time, the read received data will be output at a timing delayed by three frames or more from the written phase. Further, the frame phases of the received data outputted from the RAMs 5 and 6 are outputted to the data selection circuit 13 at the same timing. The data selection circuit 13 selects and outputs the received data from the RAM 5 or 6 in accordance with the data selection signal from the alarm control circuit 12.

Since the alarm control circuit 12 does not output alarm signals from the receiving circuits 1 and 2,
A data selection signal is output to select and output received data from AM5 or AM6, but if a failure such as loss of synchronization occurs from receiving circuit 1 and an alarm signal is output, reception from RAM6 A data selection signal is output to select data, and if a failure such as out of synchronization occurs from the receiving circuit 2 and an alarm signal is output, the RAM 5
A data selection signal is output to select the received data.

In this way, when a failure such as loss of synchronization occurs in receiving circuit 1 or 2, a data selection signal is output from alarm control circuit 12 so that normal received data is output from data selection circuit 13. At this time, the received data output from RAMs 5 and 6 is output at a timing delayed by three frames or more from the written phase, so the reception circuit 1 or 2 detects the occurrence of a failure, outputs an alarm signal, and selects the data. At the time when the circuit 13 switches the received data to be selected according to the data selection signal from the alarm control circuit 12,
This means that the RAM 5 or 6 is outputting normal received data three or more frames earlier than the written received data. Therefore, the data selection circuit 13 always outputs normal received data.

[Effects of the Invention] According to the present invention, there is no deterioration in the transmission quality of received data when a fault occurs in one of the duplex transmission paths and the selection of received data is switched. Normal data can always be output.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
5 is a timing chart showing the operation shown in the figure. 1.2...Reception circuit 3.4...Frame phase detection circuit 5.6...Dual port memory 7.8...Write address control circuit 9.10...
Read address control circuit 11...phase comparison circuit 12...alarm control circuit 13...data selection circuit

Claims (1)

[Claims] 1. A receiving circuit that recovers data and clock from received data and detects failures such as out-of-synchronization of received data;
A dual port memory in which data can be written and read arbitrarily, an address control circuit that generates a write address signal for the dual port memory from a clock of the receiving circuit, and an address that generates a read address signal for the dual port memory from a reference clock. It has two circuits consisting of a control circuit and a frame synchronization circuit that identifies a received frame number from received data, and generates the reference clock by comparing received frame number identification signals from each of the frame synchronization circuits. a data selection circuit that selects the output of each of the dual port memories using a data selection signal; and an alarm control circuit that receives an out-of-synchronization signal from each of the receiving circuits and outputs the data selection signal. When the receiving circuit detects out-of-synchronization, the alarm control circuit outputs a data selection signal for selecting normal data, and generates a write address signal to the dual port memory. A frame phase synchronization circuit characterized in that a phase difference between an address control circuit and the address signal that generates the read address signal is three or more frames of received data.