JP2856470B2 - Duplex configuration switching method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is intended to secure reliability in data transmission.
The present invention relates to a duplex configuration switching method in which a duplex unit for data communication has a duplex configuration.

[Conventional technology]

Conventionally, in data communication, two duplexers are provided to
When a duplex configuration is used, switching from one of the duplex configurations to the other is a switching method of switching by a relay, a selector, or the like.

[Problems to be solved by the invention]

The conventional switching method described above has a drawback that an error occurs at the time of switching due to a relative delay amount difference of the duplexing unit and a switching response time with respect to switching of the duplexing unit.

An object of the present invention is to provide a duplex configuration switching method capable of eliminating such disadvantages and performing error-free switching when switching a duplex unit.

[Means for solving the problem]

The present invention relates to a duplex configuration switching method including two systems of duplex units, and sends data to the two systems of duplex units in a frame configuration.
The data is separated from the frame-structured data sent from the duplexer, and the separated data is stored at addresses determined so as to correlate with the frame phase so as to have a unique correspondence. It is characterized by having switching units for selecting and sending.

Further, in the present invention, each of the switching units includes: a sending unit that sends data in a frame configuration to two duplexers; and a first unit that separates data from frame-structured data sent from one of the duplexers. A first storage unit that stores data from the first separation unit at an address determined so as to correlate with a frame phase and have a unique correspondence, and a transmission unit from the other duplex unit. A second separating means for separating data from data having a frame configuration to be obtained, and a second means for storing the data from the second separating means at an address determined so as to correlate with a frame phase so as to have a unique correspondence. It is preferable to have a storage means, and a selection means for selecting and sending out the data read from the first and second storage means.

Further, in the present invention, each switching unit includes a synchronization pattern generation circuit for generating a frame synchronization pattern, and a frame synchronization pattern from the synchronization pattern generation circuit inserted into data to be sent to the duplexing unit. A synchronization pattern insertion circuit to be sent to the duplexing unit, a first synchronization circuit that detects and synchronizes a frame synchronization pattern from frame configuration data sent from one of the duplexing units, A first separating circuit for separating data from the data of the frame configuration to be transmitted in accordance with the first synchronization circuit; and a first separation circuit which is determined so as to correlate with a frame phase detected by the first synchronization circuit to have a unique correspondence. A first buffer circuit for storing the data from the first separation circuit at the same address, and a frame from the frame-structured data sent from the other duplexer. A second synchronization circuit for detecting and synchronizing the system synchronization pattern, a second separation circuit for separating data from frame-structured data sent from the other duplexer in accordance with the second synchronization circuit, A second buffer circuit for storing data from the second separation circuit at an address determined so as to be uniquely associated with a frame phase detected by the second synchronization circuit; and for reading data. Create the address of the first
It is preferable to have a read address creation circuit for sending to the second buffer circuit and a selection circuit for selecting and sending data read from the first and second buffer circuits.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a conceptual diagram of a duplex configuration switching method according to the present invention. This duplex configuration switching method includes switching units 1A and 1B and duplex units 2A and 2B.

Further, as shown in FIG. 2, the switching unit 1A includes a synchronization pattern generation circuit 11, a synchronization pattern insertion circuit 12,
Synchronizing circuits 21A and 21B, separating circuits 22A and 22B, and buffer circuit
23A, 23B, read address creation circuit 24, selection circuit 2
5 and have.

Such a duplex configuration switching method has a switching unit 1A, 1B sandwiching two systems of duplex units.
2 shows a redundant configuration.

The switching units 1A and 1B send the output from the same circuit to the duplexing units 2A and 2B, and the inputs from the duplexing units 2A and 2B have circuits for each of the duplexing units. One of the circuit outputs is selected as a signal by a signal.

The switching units 1A and 1B have a configuration as shown in FIG. 2, respectively. On the output side to the duplexers 2A and 2B, a synchronization pattern generation circuit 11 for generating a synchronization pattern, and a synchronization pattern insertion circuit 12 for multiplexing the output of the synchronization pattern generation circuit 11 as a frame synchronization pattern with input data
And a synchronization circuit 21 for detecting the above-mentioned synchronization pattern from the input data strings from the duplexers 2A and 2B and performing frame synchronization.
A, 21B and separation circuits 22A, 22B that output data excluding this synchronization pattern from the input data strings from the duplexers 2A, 2B.
, Buffer circuits 23A and 23B for storing data from the separation circuits 22A and 22B, a read address generation circuit 24 for the buffer circuits 23A and 23B, and a two-system duplex circuit based on a switching control signal for the duplexers 2A and 2B. Of the input data from the conversion units 2A and 2B
And a selection circuit 25 for selecting a system.

Next, the operation of the duplex configuration switching method will be described.

The switching unit 1A receives n-bit input data. As shown in FIG. 2, the switching unit 1A adds a pattern generated by the synchronization pattern generation circuit 11 to the n bits of the input data as a frame synchronization pattern by the synchronization pattern insertion circuit 12, and the duplexing unit 2A , 2B. In other words, the data in the frame configuration is
It is sent as output to A and 2B.

On the other hand, an input data sequence which is an input of a frame configuration from the duplexer 2A is applied to the synchronization circuit 21A and the separation circuit 22A. Further, an input data string which is an input from the duplexer 2B is applied to the synchronization circuit 21B and the separation circuit 22B.

The synchronization circuit 21A synchronizes by detecting a synchronization pattern from the input data sequence from the duplexing unit 2A, and accordingly, the separation circuit 22A separates and outputs a data sequence corresponding to the input data sequence. This data string is written to the address of the buffer circuit 23A which is determined so as to correlate with the frame phase detected by the synchronization circuit 21A so as to have a unique correspondence. That is, the write address in the buffer circuit 23A is determined so as to correlate with the frame phase and to have a unique correspondence. Here, the frame length and the buffer capacity are not less than the difference between the delay amounts between the duplex units and the uncertain time length related to the switching.

Similarly, an input data sequence which is an input from the duplexing unit 2B becomes a data sequence by the synchronization circuit 21B and the separation circuit 22B,
This data string is written to the buffer circuit 23B.

The read address creation circuit 24 creates an address cyclically in synchronization with the input data from the duplex unit. Duplexing section
The data in the buffer circuits 23A and 23B are read according to this read address for both the data strings from 2A and 2B. The read data is selected by the selection circuit 25 by the switching control signal, and is output as output data.

Here, for example, the data from the duplexing unit 2A is
It is assumed that the output data is selected by. Duplex 2A
When switching to the duplexing unit 2B with the switching control signal from
The write addresses of the buffer circuits 23A and 23B are determined so as to correlate with the frame phase and have a unique correspondence,
On the other hand, since the read address is unique irrespective of the duplexers 2A and 2B, no error occurs during selection switching.

Such an operation is the same in the switching unit 1B.

As described above, in the duplex configuration switching method according to the present embodiment, the synchronous pattern generation circuit is provided on the output side to the duplex unit.
A synchronization pattern insertion circuit for multiplexing the output of the synchronization pattern generation circuit as a frame synchronization pattern with the input data, and detecting the synchronization pattern on the input side from the duplexing unit and performing frame synchronization. And two sets of a separation circuit and a buffer circuit for outputting data excluding the synchronization pattern from the input data string from the duplexer, and a read address generation circuit for the buffer circuit, and a switching control signal for the duplexer. And a selection circuit for selecting one of the input data from the two duplexers.

Thereby, the data transmitted / received to / from the duplexer is framed, and the write address in the buffer circuit is determined so as to be uniquely associated with the frame phase.
By making the read address unique irrespective of the duplexing unit, switching can be performed without error.

〔The invention's effect〕

As described above, according to the present invention, data to be transmitted / received to / from the duplexer has a frame structure, and a write address for data storage is determined so as to correlate with a frame phase so as to have a unique correspondence. It is unique regardless of any of the overlapping units, and there is an effect that switching can be performed without error.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram showing one embodiment of a duplex configuration switching method according to the present invention, and FIG. 2 is a block diagram showing an example of a switching unit in FIG. 1A, 1B Switching unit 2A, 2B Duplexing unit 11 Synchronization pattern generation circuit 12 Synchronization pattern insertion circuit 21A, 21B Synchronization circuit 22A, 22B Separation circuit 23A, 23B Buffer Circuit 24 ... Read address creation circuit 25 ... Selection circuit

Continuation of front page (72) Inventor Jin Kitamura 3-20-4 Nishi-Shimbashi, Minato-ku, Tokyo Japan Electric Engineering Co., Ltd. (56) References JP-A-1-125139 (JP, A) JP-A-63- 90237 (JP, A) JP-A-60-134532 (JP, A) JP-A-60-125031 (JP, A) JP-A-61-89728 (JP, A)

Claims (3)

(57) [Claims] 1. A duplex configuration switching method comprising two systems of duplexers, wherein data to the two systems of duplexers is transmitted in a frame configuration and transmitted from the two systems of duplexers. The data is separated from the data of the frame structure to be transmitted, and the separated data is stored at an address determined so as to correlate with the frame phase so as to have a unique correspondence, and the stored data is shared by a common read address signal. And a switching unit for selecting and sending one of the data read in step (1). 2. The switching unit according to claim 1, further comprising: transmitting means for transmitting data in a frame configuration to two systems of duplexers; and a first separation unit for separating data from frame-structured data transmitted from one of the duplexers. Means, first storage means for storing data from the first separation means at an address determined so as to correlate with a frame phase so as to have a unique correspondence, and a frame sent from the other duplexer. Second separating means for separating data from data having a configuration, and second storing means for storing data from the second separating means at an address determined so as to correlate with a frame phase and to have a unique correspondence. 2. The duplex configuration according to claim 1, further comprising: a selection unit that selects and sends one of data read from the first and second storage units by a common read address signal. Toggles system. 3. The switching unit includes: a synchronization pattern generation circuit for generating a frame synchronization pattern; and a frame synchronization pattern from the synchronization pattern generation circuit inserted into data to be sent to a duplexing unit.
A synchronization pattern insertion circuit to be sent to the duplexer; a first synchronization circuit that detects and synchronizes a frame synchronization pattern from frame-structured data sent from one of the duplexers; A first separation circuit that separates data from the frame configuration data according to the first synchronization circuit, and is determined so as to correlate with a frame phase detected by the first synchronization circuit to provide a unique correspondence. Address by the first
A first buffer circuit for storing data from a separation circuit of the other, a second synchronization circuit for detecting and synchronizing a frame synchronization pattern from data of a frame configuration sent from the other duplexer, A second separation circuit for separating data from the frame-structured data sent from the multiplexing unit in accordance with the second synchronization circuit, and a frame phase detected by the second synchronization circuit is correlated with a unique correspondence. At the address determined as described above.
A buffer circuit for storing data from the separation circuit, a read address creation circuit for creating an address for reading data and sending the address to the first and second buffer circuits, 2. A selection circuit for selecting and sending one of data read from a buffer circuit using a common read address signal supplied from the read address creation circuit.
2. The duplex configuration switching method described in the above.