JPS6333360B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital time division channel device.

Digital time-division communication channels in time-division telephone exchanges are usually used with high multiplexing, so a single failure can have a large effect, so it is necessary to have a redundant configuration such as duplication to ensure reliability. It is said that In addition, in time-division communication channels with a redundant redundant configuration, a thermal backup configuration is generally used in which both systems operate simultaneously, so that switching from the active system to the backup system can be performed quickly in the event of a failure. It is true. Furthermore, in this thermal reserve configuration, in order to confirm thermal reserve, data from the time division switches of both systems are collated to detect failures. on the other hand,
Since the time division highway that serves as the input/output of the time division communication path is originally a single system, the time division connector device that connects the time division highway and the time switch transfers data from the single time division highway to the duplex system. A function to select one of the data from the dual time division switch or from the dual time division switch, that is, the active system, and send it to the single time division highway, and the data from the dual time division switch. A matching function is required.

FIG. 1 is a block diagram of such a time-division channel device. The call data transmitted on the time division highway is supplied to the time division connector device 13, which is connected to a duplex time division switch 211 consisting of duplex time switches 15, 16, 17, 18 and space switches 19, 20. , 22 for exchange.
In addition, in the duplex system, the duplex time division switch 21
is the 0 system, and the duplex time division switch 22 is the 1 system. Therefore, the time switches 15 and 17 and the space switch 19 that constitute the duplex time division switch 21
is for the 0 system, and the time switches 16 and 18 and the space switch 20 that make up the duplex time division switch 22 are for the 1 system.

Now, the exchanged data is sent out from the time division switches 21 and 22 of both systems, enters the time division connector device 14 again, selects only the data from the active system time division switch, and is sent to the time division highway 12. Ru. During this time, data is transferred within the duplex time division switch in synchronization with the clocks via the clock distribution routes corresponding to each system. On the other hand, the time-sharing connector devices 13 and 14 are single-layered.
The data within is provided with a time division highway and interface using one clock. For this reason, in the time division connector device, in order to correctly distribute data to the time division switches of both systems, or to correctly collate data from the time division switches of both systems, the data synchronized with the 0 system clock,
It is necessary to perform phase matching for data synchronized with the 1st system clock.

FIG. 2 is a block diagram of a communication path device mainly consisting of the system handling the clock described above. In the figure, the time division connector devices 13 and 14 in FIG. 1 are grouped together as a time division connector device 31. Further, the functions of the time division switches 21 and 22 are divided into time division switches 32 and 33 for ease of understanding. The time division connector device 31 consists of retiming flip-flops FF 38, 43, and 44, a clock selector 37, a data selector 45, and a collation unit 46. The 0-system time division switch 32 consists of a 0-system clock distribution device 35 and retiming FFs 39 and 41. The 1-system time division switch 33 consists of a 1-system clock distribution device 36 and retiming FFs 40 and 42. The 0-system time division switch 32 and the 1-system time division switch 33 receive a clock from a common clock source 34 as input. FF3 for timing
8, 39, 40, 41, 42, 43, and 44 have a function of adjusting timing. The output clocks of the clock distribution devices 35, 35 are output from the clock selector 37.
and under the command of the selection command signal S1, the clock selector 37 selects the clock distribution devices 35, 36.
Select one of the two output clocks of FF
Control clocks 38, 43, and 44 are output.
In the figure, as shown by the dotted line, the 0-system clock distribution device 3
5 output clock is selected. The output data of FF38 is distributed to FF39 and FF40. The output data of FF41 and FF42 is FF43,
44 to the data selector 45. The data selector 45 is based on the instruction of the selection command signal S2.
Select the output of either FF43 or FF44.
In the figure, the output of FF43 is selected. A collation device 46 collates the outputs of the FFs 43 and 44. in general,
The clock distribution route in the time-division communication path constituted by duplex time-division switches is determined based on the clock phase within each system, ease of management, etc. Further, the variation in the phase difference between the clock and data arriving at the time division connector device between the two systems is usually much larger than that within each system. Variation in the phase difference between the clocks of both systems becomes a problem when retiming the FFs 40 and 44.

Problems related to the clock will be explained below. Time division connector device 3 from time division highway
1 is retimed by FF38. This retiming is performed by the 0 system clock distribution device 35 via the clock selector 37.
This is done by the system's clock. The retimed FF38 data is transferred to the FF3 in the 0-system and 1-system time division switches 32 and 33 by inter-device transmission.
9. Sent to FF40. Since retiming in the FF 39 is performed using the 0 system clock of the 0 system clock distribution device 35, no particular problem occurs.
Retiming in the FF 40 is performed by the 1-system clock of the 1-system clock distribution device 36. FF38 retiming uses the 0 system clock, FF40 retiming uses the 1 system clock, and FF38 and FF40
Since the clocks are different between the two, various problems arise. Normally, this inter-device transmission is 1/2 phase transmission or in-phase transmission. However, if the phase difference variation between both system clocks exceeds 1/2 bit, FF40
The retiming is not performed correctly, causing bit misalignment, and thermal reserve configuration cannot be guaranteed.
Conversely, a similar problem occurs between the FF 42 in the 1-system time division switch 33 and the FF 44 in the time division connector device. In other words, the retiming of FF42 is 1
This is because the retiming of the system clock and FF44 is the 0 system clock. As a result, the verifier 46 no longer performs correct verification.

The above problems become more serious as the time-division communication paths become more highly multiplexed.
This problem becomes more serious as the bit rate increases, and as more flexible implementations are sought that take into account expandability and the like.

Conventionally, in order to deal with these problems, clock distribution and retiming systems were configured using high-speed elements with little delay variation based on careful timing calculations. However, it has been subject to limitations such as high power consumption, the need for multiple types of power sources, and a reduction in the degree of freedom (for example, cable length) in the clock distribution system.

SUMMARY OF THE INVENTION An object of the present invention is to provide a digital time-division channel device that is capable of absorbing clock phase differences.

The gist of the present invention is that duplicated buffers are provided in the time division connector device, and the duplicated buffers are used in association with the 0 system and 1 system, respectively. The present invention will be explained in detail below with reference to the drawings.

FIG. 3 is a diagram showing an embodiment of a time-division channel device having a duplex configuration according to the present invention. The time division connector device 51 consists of buffers 58, 59, 60, 61, a clock selector 37, a data selector 45, and a comparator 46. The time division switch 52 of the 0 series is FF39, 41,
It consists of a system 1 clock distribution device 35. The 1-system time division switch 53 consists of FFs 40 and 42 and the 1-system clock distribution device 36. The common clock source 34 is
This is the clock source for the 0 and 1 systems.

Each buffer 58, 5 in the time division connector device
9, 60, and 61 are controlled by two clocks WCK and RCK input from the outside. Clock WCK is a clock for writing data into the buffer, and clock RCK is a clock for reading data from inside the buffer. Each buffer 58, 59
WCK and RCK of 60 and 61 are the clock outputs of the selector 37. Therefore, Batsuhua 58, 59
writes the same data at the same clock timing. Buffers 60 and 61 read written data at the same clock timing. Furthermore,
RCK of Batsuhua 58, WCK of Batsuhua 60 is 0
RCK of buffer 59 and WCK of buffer 61 are system clocks. Therefore,
Data reading from the buffer 58 and data writing to the buffer 60 are performed using the 0 system clock, which is the same clock, and data reading from the buffer 59 and data writing to the buffer 61 are performed using the 1 system clock, which is the same clock. It is carried out by. Furthermore, the output data of buffer 58 is FF39.
The output data of buffer 59 is sent to FF40.
sent to. Further, the input data to the buffer 60 is the output data of the FF 41, and the input data to the buffer 61 is the output data of the FF 42.

Explain the operation. Data input from the time division highway to the time division connector is transferred to buffers 58 and 59 installed corresponding to the time division switches of both systems.
input in synchronization with the current system clock. On the other hand, the output data from this buffer 58 is read out in synchronization with the 0 system clock and sent to FF39 of the 0 system time division switch.
The output data from the buffer 59 is read out in synchronization with the 1st system clock and sent to the FF of the 1st system time division switch.
40. Next, in order to send data from the time division switch to the time division highway, the 0 series data is sent from the FF 41 to the buffer 60, and the 1 series data is sent from the FF 42 to the buffer 61. At this time, the write clock to the buffers 60 and 61 is performed by the output of the selector 37, and data reading from the buffer 60 and data reading from the 0 system clock buffer 61 is performed by the 1 system clock.

According to the above operation, when data is taken in from the time-division highway, the phase difference between the input and output clocks is absorbed by the buffers 58 and 59, and the data is synchronized from the working system clock to each system clock. On the other hand, when sending data to a time-division highway, data is transmitted between devices using a system-compatible clock, and then buffered at 6
It is synchronized with the working system clock at 0.0, 61 and output to the time division highway, or verified by the verification unit 46. This allows the redundant time division switch and one
At the interface with the multiplexed time-sharing connector device, it is possible to achieve phase matching between the clocks of each system and the working system clock, even if there is a phase difference between the clocks of both systems arriving at the time-sharing connector device. Even if there is variation, no bit shift occurs.

The buffers 58, 59, and 60h61 have the same configuration. FIG. 4 is a diagram showing an embodiment of such a buffer having the same configuration. Figure 5 is the time chart. Batsuhua is FF10, 11, 12,
It consists of a selector 13 and frequency dividing circuits 14 and 15. The FFs 10 and 11 on the A side are controlled by the clock CK obtained from the output of the frequency dividing circuit 14, and the FF 12 and selector 13 on the B side are controlled by the output clock from the frequency dividing circuit 15. . The input of the frequency dividing circuit 14 is the clock WCK, and the input of the frequency dividing circuit 15 is the clock RCK.

Input data 1 (D0, D1, D2, ...) is sent to FF10, synchronously with the output clock of frequency dividing circuit 14.
Time division classification into 11 (D0, D2, D4,...,
and D1, D3, D5,...) and stored. Clocks 2 and 3 are frequency-divided to have twice the frequency of clock WCK0, and are classified according to the clocks having twice the frequency. Thus, FF10 and 11
For outputs 4 and 5, the data determination width is doubled, that is, the width is 2 bits. Next, this data having a defined width of 2 bits is selected by a selector 13 which performs selection control using a clock 7. Selector 13
The output of is taken into FF12 by clock 6 and output 9 is generated. In this case, as is clear from the time chart in Figure 5, even if the phase difference between the clocks on the A side and the clocks on the B side varies by about ±1 bit, the data can be synchronized with the clocks of each system without causing a bit shift. Can be synchronized.

In the above embodiment, an example has been shown in which variations in clock phase difference up to ±1 bit are absorbed, but it goes without saying that this can generally be expanded to ±N bits. Also, as the third clock, 0
Needless to say, the present method using a working system clock selected from the system clocks and the clocks of the first system is also generally applicable to the case where a third clock via a separate distribution route is used.

According to the present invention, the constraints that were conventionally necessary to prevent bit shifts due to phase difference variations between the clocks of both systems that occur at the junction between the duplexing section and the singlexing section, ie, the clock distribution system and retiming system, can be improved. It has become possible to eliminate restrictions on the elements used in the system, as well as implementation restrictions such as cable length restrictions in the clock distribution system. Furthermore, this has the effect of reducing the power consumption of the device and the type of power source.

[Brief explanation of drawings]

1 and 2 are conventional examples, FIGS. 3 and 4 are examples of the present invention, and FIG. 5 is a time chart. 51... Time division connector device, 52, 53... Time division switch, 58, 59, 60, 61... Buffer circuit.

Claims (1)

[Claims] 1. A time division connector device, a 0 system time division switch, and a 1 system time division switch, and
A first interface unit is an interface unit with the 0-system time-division switch in the time-division connector device, and is an interface unit for transmitting data from the time-division connector device to the 0-system and 1-system time-division switches.
The interface unit for receiving data from the 0-system and 1-system time-division switches of the time-division connector device is constituted by third and fourth buffers, and the first buffer is The second buffer serves as a buffer for transfer to the 0-system time-division switch, the third buffer serves as a buffer for transfer to the 1-system time-division switch, and the third buffer serves as a buffer for reception from the 0-system time-division switch. 4's battle is 1
It is used as a buffer for receiving data from the time division switch of the system, as well as a clock for determining timing for writing input data to the first and second buffers, and a clock for determining timing for reading data from the third and fourth buffers. The clock is formed by time-division clocks formed by the same clock, and the clock for determining the read timing of the first buffer and the clock for determining the write timing of the third buffer are connected to the 0-system time-division clock. The clock for determining the read timing of the second buffer and the clock for determining the write timing of the fourth buffer are formed by the clock from the switch.
1. A digital time division communication channel device characterized in that it is formed by a clock from a time division switch of a system. 2. The digital time-division channel device according to claim 1, wherein the same clock is a working clock selected from among the clocks of a 0-system or 1-system time division switch. 3. A patent claim characterized in that the above-mentioned same clock is provided from another clock source having the same period and same pulse width as the working system clock selected from among the clocks of the 0-system or 1-system time division switch. The digital time division communication device according to item 1.