JPH0736632B2 - Time slot shift control system - Google Patents

Description

The present invention relates to a control system for shifting a time slot in use in a communication system using time slot multiplexing,
In particular, the present invention relates to a control method for dynamically controlling a signal frame communication area of both communications in a hybrid communication system of time slot multiplex type communication and burst type communication.

[Conventional technology]

In a communication system having a hybrid configuration of circuit switching type communication and burst type communication using time slot multiplexing, the circuit switching communication area and burst communication area of a signal frame are dynamically controlled according to the traffic of both communications. This is extremely effective for efficient use of the transmission line.

A conventional example of such a communication control system will be described with reference to FIG. 11 and FIG. The transmitting device and the receiving device synchronize with the synchronization signal F.
The communication is performed in the signal frame of the period T0 started at 1. The circuit switching communication area and the burst communication area are separated by the partition signal BD, and the circuit switching communication area is further divided into a plurality of time slots. Introduction, No. 11
It is assumed that the state shown in FIG. That is, it is assumed that the first, third, and fourth time slots in the circuit-switched communication area are used for the circuit-switched signals Z, Y, and X, respectively, and the second time slot is empty. In this case, in order to use the transmission line efficiently, the circuit-switched signal X using the last time slot is shifted to the second time slot, and as shown in FIG. However, conventionally, this is done by the procedure shown in FIG. The transmitting device sends a time slot shift request signal, and the receiving device shifts the time slot of the circuit switching signal X based on this request signal and then returns a response signal. The transmitter shifts the time slot at the same time as receiving the response signal. In this case, the transition from the state A shown in FIG. 11 (a) to the state C in FIG. 11 (c) is performed based on the reception of the response signal at the transmitting device and the transmission of the response signal at the receiving device. In this transition control, both devices need to be synchronized in time.

[Problems to be solved by the invention]

However, in this control method, for example, when there is a transmission error in the response signal, the receiving device performs the time slot shift control, but the transmitting device does not perform this, which results in a mismatch. There is a problem in terms of reliability. In addition, the control becomes complicated because it is necessary to be aware of the time when transmitting / receiving / processing these signals.

The present invention implements time slot shift control of a circuit-switched communication part in an integrated communication system in which circuit-switched communication and burst-type communication are multiplexed on the same line.
When an empty slot occurs in the circuit-switched communication part, the empty time set is shifted to the rear end of the signal frame so that the shifted empty time slot is used for burst communication, and between the circuit-switched communication and burst communication. The present invention provides a time slot shift control method for a circuit-switched communication part to dynamically exchange transmission band and implement an efficient integrated communication system.

[Means for solving problems]

According to the time slot shift control method of the present invention, in a communication system that performs time slot multiplex communication between a transmitter and a receiver, a time slot multiplex signal is added with information indicating its length by using a variable length signal frame. When a vacant time slot is generated, the transmitter communicates with the vacant second time slot to be shifted with respect to a certain line signal using the first time slot located behind this vacant time slot and the second time slot. A time slot shift request signal that transmits the line signal redundantly using one time slot and notifies the receiving device that the line signal of the first time slot is to be shifted to the second time slot. Based on the time slot shift request signal, the receiving device sets the reception time slot of the line signal to the first time slot. From the time slot of the second time slot to the second time slot and sends a response signal indicating that the shift control is completed to the transmission device, and when the transmission device receives the response signal, the transmission device transmits the line signal to the second time slot. In the case where only the slots are provided and the vacant first time slot is the rear end time slot in the variable-length signal frame, information indicating the signal length of the signal frame is added to the first time slot. Is set to the deleted length and the first time slot is converted to the deleted signal frame and transmitted.

〔Example〕

FIG. 1 shows a communication device used in the present invention, which has a transmitter and a receiver. In the transmitter, signals from the subscriber interface circuits 101, 102, 13 for transmitting the circuit-switched communication terminal are transmitted via the bus 100 to the transmission buffer 11 for the circuit-switched communication.
After being temporarily stored in the transmission line 1, it is transmitted to the transmission line 1 through the multiplexing circuit 19. Writing from the subscriber interface circuits to the transmission buffer 11 is controlled by the write control circuit 13, and reading from the transmission buffer 11 to the transmission line 1 is controlled by the read control circuit 14. Signals from the subscriber interface circuits 111, 112, 113 for transmitting burst communication terminals are transmitted via the bus 110 to the transmission buffer 12 for burst communication.
After being temporarily stored in, the data is sent to the transmission line 1 via the multiplexing circuit 19. Writing to and reading from the transmission buffer 12 are performed by the control circuit 15. The write control circuit 13 specifies the subscriber interface circuit to be written in the transmission buffer 11 based on the counter 16 which counts at a constant cycle T0, and similarly the read control circuit 14 in the transmission buffer 11 to be transmitted to the transmission line 1. Identify the signal. Multiplexing control circuit 20
Is for multiplexing the transmission signals. When the counter 16 indicates the start of the cycle T0 by the control signal 16-1, the multiplexing circuit 19
To send the synchronizing signal F in the register 17, and subsequently to send the multiplexed circuit-switched signal in the transmission buffer 11. The read control circuit 14 performs transmission control based on the output value of the counter 16, and when it detects the end of transmission of the circuit switching communication signal, it notifies the multiplexing control circuit 20 of that fact by the control signal 14-1. Based on this, the multiplexing control circuit 20 sends the partition signal BD in the register 18 and then the transmission buffer
Start sending burst communication signals within 12. These multiplex controls are performed by the control signal 20-1. The series of controls are repeated every cycle T0. That is, the synchronization signal F, the circuit switching communication data, the partition signal BD, and the burst communication data are transmitted to the transmission line 1 in this order at every cycle T0.

Next, the operation of the receiver will be described. The signal received via the transmission line 2 is supplied to the signal detection circuit 28 and the separation circuit 29. When the signal detecting circuit 28 detects the synchronizing signal F, the counter 26 is initialized by the control signal 28-1 to establish the synchronization, and the separating circuit 29 is controlled by the control signal 28-2 to receive the received signal for circuit switching communication. It is supplied to the reception buffer 21. When the partition signal BD is detected, the reception signal is controlled to be supplied to the reception buffer 22 for burst communication. Writing from the transmission path 2 to the receiving buffer 21 for circuit switching and reading from the bus 200 are performed by the write control circuit 24, respectively.
And the read control circuit 23. The received circuit switching signal sent to the bus 200 is supplied to the subscriber interface circuit specified by the read control circuit 23 among the subscriber interface circuits 201, 202 and 203 for receiving the circuit switching communication terminal. On the other hand, the receive buffer for burst communication 22
Under the control of the control circuit 25, specifically, the received data therein is based on the destination address of the packetized received burst signal, and the subscriber interface to be received from the receiving subscriber interface circuits 211, 212, 213 of the burst communication terminal. The face circuit is identified and the received signal is supplied via the bus 210.

The above is the flow of the transmission signal and the reception signal in this communication device. Next, referring to FIG. 2 and FIG.
An example will be described. In the transmission side communication device of the present embodiment, the write control circuit 13 of the transmission buffer 11 has a control memory, specifies the subscriber interface circuits 101, 102, 103 based on the count value of the counter 16, and transmits the transmission signal thereof. Write in place in The read control circuit 14 also has a control memory, and the line switching signals in the transmission buffer 11 are transmitted in the transmission line 1 in the order written therein.
Send to. As shown in FIG. 2, it is assumed that the state A is first shown in FIG. 11 (a). FIG. 3A shows the contents of the transmission buffer 11 of the transmitter and the contents of the control memory of the write control circuit 13 and the read control circuit 14 at this time. In the receiving side communication device, the receiving circuit switching signal is stored in the receiving buffer 21 at the address position written in the control memory in the writing control circuit 24, and the reading control circuit.
The signals in the reception buffer 21 are read out to the bus 200 and supplied to one of the subscriber interface circuits 201, 202 and 203 in the order written in the control memory 23. Similarly, FIG. 3A shows the contents of the reception buffer 21, the contents of the control memory of the write control circuit 24 and the read control circuit 23. The circuit switching control circuit 10 controls the control signals 10-1, 10-2, 10-3,
According to 10-4, the write control circuit 13 of the transmission buffer 11, the read control circuit 14, the write control circuit 2 of the reception buffer 21.
4. The read control circuit 23 controls each control memory. The circuit switching control circuit 10 is connected to the buses 110 and 210 and uses the burst communication area to perform circuit switching control communication with the circuit switching control circuit of the partner communication device.

In the FIG. 3 (a), in accordance with the contents of the write control circuit 13, the second bus 100, fifth, fourth time slot in circuit switching signal X, Y, Z address #X _1, # Y ₁ , #Z ₁ is the buffer area in the transmit buffer 11, that is, the second,
3, written in the 4th area respectively. Transmission line 1
To the read control circuit 14. That is, the signal Z of Introduction #Z ₁ area, the third, the area #Y ₁ as the fourth circuit-switched signals, signals Y # X _1, X is sent. In this case, the second area was in use until just before, but is now empty due to the call termination. When the read control circuit 14 outputs the END signal indicating the end of the circuit switching communication area, this is supplied to the multiplexing control circuit 20 by the control signal 16-1. Multiplexing control circuit 20 is a control signal
The partition signal BD in the register 18 is sent to the transmission line 1 by 20-1 and the packetized burst signal stored in the transmission buffer 12 for burst communication is continuously transmitted to the transmission line 1.
Send to. Therefore, the signal shown in FIG. 11 (a) is transmitted to the transmission line 1. On the receiving side, the write control circuit 24 informs the address #X ₂ , # of the area of the receiving buffer 21 in which the signals X, Y, Z should be stored corresponding to the time slot numbers of the circuit switching communication area of the received signal frame. Y ₂ and #Z ₂ are written, and each reception circuit switching signal is stored in a predetermined area of the reception buffer 21. In this case, the circuit-switched signal Z in the first time slot of the received signal frame is #Z ₂
In the area specified, third, fourth line switching signal Y, X are each #Y _2, is stored in the area of the reception buffer 21 given by # X _2. The read control circuit 23 reads the circuit-switched signal in the receiving buffer 21 in the time slot of the bus 200 assigned to each receiving subscriber interface circuit. In this case, the circuit-switched signals Z, X, and Y are transmitted on the bus 200 in the first, second, and fourth time slots.
Is supplied to.

On the transmitting side, since the second time slot is empty (idle), control for shifting the signal X of the last time slot to this time slot is started. That is,
The transition control to the state B in FIG. 2 is started. First, the second time slot of the transmission frame is set to the circuit-switched signal X.
The circuit switching control circuit 10 uses the control signal 10
The -2, as shown in FIG. 3 (b1), rewrites the second th area of the read control circuit 14 from the idle to #X _1. As a result, as shown in FIG. 11 (b), the signal X is transmitted redundantly using the second and fourth time slots of the signal frame on the transmission path 1. In this state,
Since the receiving side does not know the duplicate transmission of the signal X, the same control as in state A is performed. The circuit switching control circuit 10 on the transmitting side uses the burst communication area at the time when the rewriting of the read control circuit 14 is completed, and sends the signal X to the circuit switching control circuit on the receiving side.
The time slot shift request signal for notifying the shift to the second time slot of is transmitted. The circuit switching control circuit 10 (substituting in FIG. 1) on the receiving side receives this control signal.
Using 10-3, as shown in FIG. 3 (b2), the second area of the write control circuit 24 of the reception buffer 21 is rewritten to #X ₂ so as to receive the signal X from an empty space (idle). As a result, the signals X of the second and fourth time slots of the received signal frame are written in the area given by #X ₂ of the reception buffer 21 in an overlapping manner. in this case,
Since the data is read out to the bus 200 only once in the cycle T0, even if the reception buffer 21 receives the data redundantly, it is supplied to the subscriber interface circuit as one circuit-switched signal.

Further, the receiving side circuit switching control circuit 10 sets the fourth area of the read control circuit 24 to the # area as shown in FIG. 3 (b3).
Rewrite from X ₂ to empty (idle). This allows the
The circuit-switched signal X in the fourth time slot of the signals shown in FIG. 11 (b) is not received by the reception buffer 21.
When this rewriting is completed, the receiving side circuit switching control circuit 10
Sends a response signal back to the transmission side circuit switching control circuit 10 using the burst communication area. On the basis of the reception of this response signal, the transmission side circuit switching control circuit 10 deletes #X _{1 in the} fourth area of the read control circuit 14 of the transmission buffer 11 as shown in FIG. EN indicating the end of the communication area
Write the D signal. As a result, as shown in FIG. 11 (c), the circuit-switched communication area becomes shorter and the partition from the burst communication area shifts forward of the signal frame.

In the present embodiment, since it is not necessary to perform the state transition between the transmitting side and the receiving side in synchronization (time adjustment), for example, it is assumed that there is a transmission error in the response signal from the receiving side. Can be recovered by retransmission control. in this case,
Only the state shown in FIG. 3 (b3) is lengthened, and communication of the signal X is not hindered. In the present embodiment, if a write time slot from the bus 100 of the transmission buffer 11 or a read time slot from the receive buffer 21 to the bus 200 is fixedly assigned to each subscriber, a write control circuit is provided. The read control circuit 23 may use the outputs of the counter 16 and the counter 26 as they are.

Next, a second embodiment of the present invention will be described with reference to FIGS. In this embodiment, the transmitting side is the same as the first embodiment, but the function of the receiving side is different. On the reception side, the write control circuit 24 of the reception buffer 21 has only the function of causing the reception buffer 21 to receive the signal of the circuit switching communication area as it is. Therefore, the reception buffer 21 receives all the circuit-switched signals of FIG. 11 (a) as shown in FIG. 3 (a). The read control circuit 23 reads the stored circuit-switched signal according to its contents. That is, the first bus 200,
Receive buffer 21 at the 2nd and 4th time slots
The circuit-switched signals Z, X, Y in the area given by # Z ₂ , # X ₂ , and # Y ₂ in Similar to the first embodiment, the transmitting side sends the signal X in a duplicated state as shown in FIG. 3 (b1). The contents of the reception buffer 21 at this time are shown in FIG. 4 (b1). The receiving side shifts to the state of FIG. 4 (b2) based on the time slot shift request signal of the circuit switching signal X from the transmitting side. That is, #X ₂ of the read control circuit 23 is rewritten to #X ₂ ′. As a result, the circuit-switched signal X in the second area in the reception buffer 21, that is, given by #X ₂ 'is supplied to the subscriber interface circuit as the second time slot signal on the bus 200. After this control is completed, the circuit switching control circuit 10 on the receiving side returns a response signal to the circuit switching control circuit 10 on the transmitting side. When the transmitting side receives this response signal, the contents of the read control circuit 14 are rewritten and the state shifts to the state shown in FIG. 4 (c). This state on the transmitting side is the same as in the first embodiment.

Next, a third embodiment of the present invention will be described with reference to FIGS. This embodiment is the same as the first embodiment on the receiving side, but the function on the transmitting side is different. On the transmitting side, as shown in FIG. 5 (a), the line switching signals X, Y, Z are the second, fifth and fourth time slots on the bus 100 based on the contents of the write control circuit 13. using, #X ₁ of the transmission buffer 11, # Y _1, is stored in the area designated by # Z _1. In this case, this write control will
The transmission signal frame is organized within 11. That is, the signal in the transmission buffer 11 has the same structure as the signal frame in the circuit switching communication area shown in FIG. The read control circuit 14 holds the number of time slots of the circuit-switched signal to be transmitted. In FIG. 5 (a), N (= 4) is set, and the signal shown in FIG. 11 (a) is Sent out. In this case, when the read control circuit 14 sends out the circuit switching signals of N time slots, the multiplexing control circuit 20
And the partition signal BD is sent. In the state shown in FIG. 5 (b1), on the transmitting side, the empty time slot of the bus 100 is set to the empty area of the transmission buffer 11 by using the first time slot in order to redundantly transmit the circuit switched signal X. Is written in the second area. Specifically, #X ₁ ′ is written in the _first area of the write control circuit. As a result, the transmission line switching signal X uses the first and second time slots of the bus 100 for #X ₁ and #.
Each is written in the area given by X ₁ ′.
Therefore, the signal shown in FIG. 11 (b) is transmitted to the transmission line 1. When the receiving side receives the time slot shift request signal from the transmitting side, it performs the same control as that of the first embodiment, and after passing through the states shown in FIGS. 5 (b2) and 5 (b3), returns the response signal. Will be returned. On the transmission side, when the response signal is received, the write control circuit 13 erases the second data #X ₁ as shown in FIG. As a result, the circuit-switched signal X is written in the transmission buffer 11 only by the first time slot of the bus 100. In this embodiment, the time slot in the bus 100 on the transmission side is also shifted according to the time slot shift control on the transmission line 1. However, if the time slot on the bus 100 is to be returned to the original time slot, the transmission side further pre-shifts. It is sufficient to write #X ₁ ′ in the second area of the write control circuit 13 which is the position of, and then make the first area empty.

Referring to FIGS. 1 and 6, the fourth embodiment uses the receiving side of the second embodiment and the transmitting side of the third embodiment. That is, the transmission signal frame of the circuit-switched communication area is organized in the transmission buffer 11, this signal frame is received as it is in the reception buffer 21, and the time slot shift control is performed to the same transmission buffer 11 as in the third embodiment. Write control and the same receive buffer 21 as in the second embodiment
It is realized by the read control of.

In each of the above embodiments, the partition between the circuit-switched communication area and the burst communication area is given by the partition signal BD, but instead of this, information for giving the length of the circuit-switched communication area immediately after the synchronization signal F is partitioned. It may be sent as information. Further, in the configuration of FIG. 1, the only component newly added to the communication device in order to implement the present invention is a part that sends out partition information at every cycle T0 and detects reception thereof. A communication function between circuits and a function of controlling a write control circuit and a read control circuit of each buffer are provided as basic functions of the communication device. Therefore, the time slot shift control can be realized by adding an extremely simple circuit. With respect to burst communication, a partition signal indicating the area is transmitted at every cycle T0, so that the burst communication area can always be specified even if the partition changes. Further, control signals such as a time slot request signal and a response signal may be transmitted and received by the circuit switching communication area.

The present invention is not limited to the one-to-one communication as described above,
It can also be applied to 1 to N, and further to N to N communication systems as shown in FIG. FIG. 7A shows a loop-shaped transmission line 30.
Shows a network in which a plurality of nodes 31 to 36 are connected with each other, and FIG.
Shows a network in which multiple nodes are connected. 8th
The figure shows the signals on these transmission lines, and the circuit-switched signals and burst communication signals are packetized. Here, since it is not related to the access format to the transmission lines 30 and 40, the description thereof is omitted. The structures of the circuit switching signal packet (circuit packet) and the burst communication packet (burst packet) are shown in FIGS. 9 (a) and 9 (b). Each packet is delimited by a start delimiter SD and an end delimiter ED, and has a flag C / B indicating whether it is a line packet or a burst. In a circuit packet, the information field has an AD giving a unique logical number of this packet, and the information field is composed of one or a plurality of time slots. The receiving node receives the circuit-switched signal specified by this logical number AD and time slot number. The burst packet has a structure including information INFO with a destination address DA and a transmission address SA as headers. The state of time slot shift control in this case is shown in FIG. FIGS. 10 (a), 10 (b) and 10 (c) show FIGS. 11 (a) to 11 (c).
It is a state corresponding to. In the one-to-one communication, the shift control of the time slot is performed by the synchronization signal F and the partition signal BD, whereas in the N-to-N communication using the line packet, it is only performed based on the delimiter and the logical number AD. In addition, the time slot shift request signal and the response signal may be exchanged with the receiving node that communicates using the shifted time slot.

Although the communication system in which the circuit switching communication and the burst communication are integrated has been described above as an example, the present invention can be applied to other communication systems. Multiple circuit-switched signals, specifically,
In a communication system in which 64 Kbps and 32 Kbps lines are integrated, a 64 Kbps line time slot can accommodate two 32 Kbps sub time slots. In this case, one 32Kbps line will be released depending on the line release status of the 32Kbps line.
There may be multiple time slots that can only accommodate one. In this case, if the time slot shift control according to the present invention is performed, two time slots accommodating only one 32 Kbps line can be combined into one time slot, and the number of time slots assigned to the 64 Kbps line can be increased. You can

〔The invention's effect〕

According to the present invention, in a communication system that requires time slot shift control, such as a communication system that integrates circuit switched communication and burst communication or multiple circuit switched communication, when transmitting time slot shift control, It is possible to provide a highly reliable communication system that simplifies control because it is not necessary to adjust the time between receiving devices and effectively uses signal frames.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a communication device using the present invention, and FIG.
FIG. 3 is a diagram showing a control procedure in the present invention, and FIG.
3 (c), 4 (a) to 4 (c), 5 (a) to 5 (c), and 6 (a) to 6 (c).
Is a diagram for explaining the first, second, third and fourth embodiments of the present invention, FIGS. 7 (a) and 7 (b) are diagrams showing another network to which the present invention is applied, FIG. 8 is a diagram showing signals on a transmission line in the networks of FIGS. 7 (a) and 7 (b), and FIGS. 9 (a), 9 (b) and 10 (a).
~ Fig. 10 (c) is a diagram showing the structure of a packet signal used in the network of Fig. 7 (a) and Fig. 7 (b), and Fig. 11 (a) to Fig. 11 (c) in the present invention. FIG. 12 is a diagram showing a state of a signal frame, and FIG. 12 is a diagram showing a control procedure in the conventional example. 1,2 ... Transmission path, 101,102,103,111,112,113,201,202,20
3,211,212,213 …… Subscriber interface circuit, 11,12,2
1,22 …… buffer, 10,13,14,15,20,23,24,25 …… control circuit, 16,26 …… counter, 17,18 …… register, 19 ……
Multiplexing circuit, 28 ... Signal detection circuit, 29 ... Separation circuit.

Claims (1)

[Claims] 1. In a communication system for performing time slot multiplex communication between a transmitter and a receiver, a time slot multiplex signal is communicated by using a variable length signal frame with information indicating its length added and transmitted. When an empty time slot occurs, the device allocates an empty second time slot and the first time slot to be shifted with respect to a line signal using the first time slot located after the empty time slot. And redundantly transmitting the line signal by using the time slot shift request signal for notifying the receiving device of shifting the line signal of the first time slot to the second time slot, and receiving The apparatus changes the reception time slot of the line signal from the first time slot to the first time slot based on the time slot shift request signal. Of the response signal indicating that the shift control has been completed is transmitted to the transmitting device, and when the transmitting device receives the response signal, the transmitting device transmits the line signal only to the second time slot and If the first time slot is a rear time slot in the variable-length signal frame, the information indicating the signal length of the signal frame is set to the length obtained by deleting the first time slot. The time slot shift control method is characterized in that the signal frame is transmitted after the first time slot is deleted.