JPS6359098A - Time slot shifting control system - Google Patents

Abstract

PURPOSE:To simplify a control and to improve the reliability by constituting a communication system which needs shift control for time slots so that the time coincidence between a transmitter and a receiver is not necessary in shift- controlling the time slot. CONSTITUTION:In the communication system of a hybrid constitution capable of time slot multiplex type communication and burst type communication, the signal frame communication areas of the both communications ape dynamically controlled. That is, the transmitter transmits data by multiplexing line signals through a multiplexing circuit 19 by using both a first time slot dedicated to line signals and a second time slot to be shifted. And a time-slot-shift-command signal to inform the number-information of a line signal to shift a time slot for the receiver and the number-information of the second time slot to be shifted, is transmitted. Eased on this shift-command signal, the receiver executes the shift control of reception time slot via a line change-over control circuit 10 in order to shift the reception time slot for line signal from the first one to the second one, then transmits to the transmitter a response signal in dicating the end of the shift control. On receiving this response signal, the transmitter limits the transmission time slot for line signal only to the second time slot.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention provides a control method for shifting time slots in use in a communication system using time slot multiplexing;
In particular, the present invention relates to a control method for dynamically controlling the signal frame communication area of time slot multiplexed communication and burst type communication in a hybrid communication system.

[Conventional technology]

In a communication system with a hybrid configuration of circuit-switched communication using time slot multiplexing and burst-type communication, the circuit-switched communication area and the burst communication area of a signal frame are dynamically controlled according to the traffic of both communications. This is extremely effective for efficient use of transmission paths.

Conventional examples of such communication control methods are shown in Figs. 11 and 12.
This will be explained with reference to the figures. The transmitting device and the receiving device communicate in a signal frame of period TO starting with the synchronization signal F, and the circuit-switched communication area and the burst communication area are separated by a partition signal BD, and the circuit-switched communication area is further divided into multiple areas. time slots. First, assume that the state shown in FIG.
First in the circuit switched communication area. Third. Assume that the fourth time slot is used for circuit switched signals z, y, and x, respectively, and the second time slot 1 is vacant. In this case, to use the transmission path efficiently, the circuit-switched signal X using the last time slot is shifted to the second time slot, and the circuit-switched communication area is expanded as shown in FIG. Although it is necessary to shorten the time, this has conventionally been done using the procedure shown in FIG. The transmitting device sends out a time slot shift request signal, and the receiving device shifts the time slot of the circuit switched signal X based on this request signal, and then returns a response signal. The transmitting device shifts the time slot at the same time as receiving this response signal. In this case, the transition from state A shown in FIG. 11(a) to state Rc shown in FIG. 11(c) is performed based on the reception of a response signal in the transmitting device, and the transmission of the response signal in the receiving device. In controlling this transition, it is necessary for both devices to synchronize the time.

[Problem that the invention seeks to solve]

However, in this control method, if there is a transmission error in the response signal, for example, a discrepancy occurs in that the receiving device performs time slot shift control while the transmitting device does not. There are problems with reliability. Furthermore, since it is necessary to be aware of the time when transmitting, receiving, and processing these signals, control becomes complicated.

[Means for solving problems]

The time slot shift control method of the present invention provides a communication system that performs time slot multiplex communication between a transmitting device and a receiving device, in which the transmitting device selects a first time slot that is used for a certain line signal and a second time slot that is to be shifted. time slot shift for transmitting the line signal redundantly using the time slot of , and then notifying the receiving device of the number information of the line signal to shift the time slot and the number information of the second time slot to be shifted; A request signal is sent, and the receiving device performs shift control of the reception time slot based on the shift request signal, shifts the reception time slot of the line signal from the first time slot to the second time slot, and then shifts the reception time slot of the line signal from the first time slot to the second time slot. A response signal indicating that the control has been completed is sent to the transmitting device, and the transmitting device that receives the response signal sets only the second time slot as the transmission time slot of the line signal.

〔Example〕

FIG. 1 shows a communication device used in the present invention, which includes a transmitter and a receiver. In the transmitting section, subscriber interface circuits 101, 102 .
After the signals from 103 are temporarily stored in the transmission buffer 11 for circuit-switched communication via the bus 100, they are sent to the multiplexing circuit 19.
The signal is sent out to transmission line 1 via the . Writing from each subscriber interface circuit to the transmission buffer 11 is controlled by the write control circuit 13.
Reading to and from each is controlled by a read control circuit 14, respectively. Signals from the subscriber interface circuits 111, 112, 113 for burst communication terminal transmission are transmitted via bus 11.
After being temporarily stored in the transmission buffer 12 for burst communication via 0, the signal is sent to the transmission line 1 via the multiplexing circuit 19. Writing to and reading from the transmission buffer 12 is performed by the control circuit 15. The write control circuit 13 specifies the subscriber interface circuit to be written to the transmission buffer 11 based on the counter 16 that counts at a constant period TO, and the read control circuit 14 similarly specifies the subscriber interface circuit to be written to the transmission buffer 11 to Identify the signal. The multiplexing control circuit 20 controls the multiplexing of transmission signals, and when the counter 16 indicates the start of period TO by the control signal 16-1, it controls the multiplexing circuit 19 and sends out the synchronization signal F in the register 17. Subsequently, the multiplexed circuit switching signal in the transmission buffer 11 is transmitted. Read control circuit 1
4 performs transmission control based on the output value of the counter 16;
When the end of transmission of the circuit switched communication signal is detected, the control signal 1
4-1, the multiplex control circuit 20 is notified of this fact. Based on this, the multiplexing control circuit 20 sends out the partition signal BD in the register 18, and then starts sending out the burst communication signal in the transmission buffer 12. These multiplexing controls are performed using the control signal 20-1, and this series of controls is repeated every cycle To. That is, the synchronization signal F1, circuit-switched communication data, partition signal BD, and burst communication data are sent out to the transmission line 1 in this order every cycle To.

Next, the operation of the receiving section will be explained. The signal received via the transmission line 2 is supplied to a signal detection circuit 28 and a separation circuit 29. When the signal detection circuit 28 detects the synchronization signal F, it initializes the counter 26 using the control signal 28-1 to establish synchronization, and also controls the separation circuit 29 using the control signal 28-1.
2 and supplies the received signal to the receiving buffer 21 for circuit switched communication. When the partition signal BD is detected, control is performed so that the reception fi3 tQ signal is supplied to the reception buffer 22 for burst communication. Receive buffer 21 for line switching
Writing from the transmission line 2 to the bus 200 and reading from the bus 200 are performed by a write control circuit 24 and a read control circuit 23, respectively. The received circuit-switched signal sent to the bus 200 is supplied to the subscriber interface circuit specified by the readout control circuit 23 among the subscriber interface circuits 201, 202, 203 for receiving circuit-switched communication terminals. On the other hand, the reception buffer 22 for burst communication
The received data is received from among the receiving subscriber interface circuits 211, 212, and 213 of the burst communication terminal under the control of the control circuit 25, specifically, based on the destination address of the packetized received burst signal. The desired subscriber interface circuit is identified and provided with the received signal via bus 210.

The above is the flow of transmission signals and reception signals in this communication device. Next, using FIGS. 2 and 3,
An example will be described. In the transmission side communication device of this embodiment, the write control circuit 13 of the transmission buffer 11
has a control memory, specifies the subscriber interface circuits 101, 102, 103 based on the count value of the counter 16, and writes the transmission signal to a predetermined position in the transmission buffer 11. The read control circuit 14 also has a control memory,
The circuit-switched signals in the transmission buffer 11 are sent to the transmission line 1 in the order written here.

As shown in FIG. 2, it is assumed that the state RA is initially shown in FIG.
1 and its write control circuit 13. The contents of the control memory of the read control circuit 14 are shown in FIG. 3(a).

In the receiving side communication device, the receiving line switching signals are stored in the receiving buffer 21 at the address positions written in the control memory in the write control circuit 24, and are received in the order written in the control memory of the read control circuit 23. The signals in buffer 21 are read out onto bus 200 and supplied to any of subscriber interface circuits 201, 202, and 203. Similarly, FIG. 3(a) shows the contents of the reception buffer 21, the contents of the control memory of the write control circuit 24, and the read control circuit 23. The circuit switching control circuit 1o receives a control signal 10-1.

Transmission buffer 11 by 10-2.10-3.10-4
Write control circuit 13. Read control circuit 14. The control memories of the write control circuit 24 and read control circuit 23 of the reception buffer 21 are controlled. The line switching control circuit 10 is also connected to buses 110 and 210, and performs line switching control communication with the line switching charge control circuit of the other communication device using the burst communication area.

In FIG. 3(a), according to the contents of the write control circuit 13, the line exchange signals x, y, z are sent to addresses #X+, # in the second, fifth, and fourth time slots on the bus 100.
Y1, the buffer area in the transmission buffer 11 given by #Z+, that is, the 2nd, 3rd, . Each is written in the fourth area.

Sending to the transmission path 1 is performed according to the contents of the read control circuit 14. That is, the signal Z in the #Z1 area is first, and the signal Z in the #Z1 area is the first signal Z in the #Z1 area. Area #'yt as the fourth circuit switched signal,
#x, signals Y and X are sent out.

In this case, the second area was in use until just before, but is now empty due to the end of the call. When the read control circuit 14 outputs an END signal indicating the end of the line-switched communication area, this is supplied to the multiplex control circuit 20 by the control signal 16-1.

The multiplexing control circuit 20 sends the partition signal BD in the register 18 to the transmission line 1 in response to the control signal 20-1, and subsequently sends the packetized burst signal stored in the transmission buffer 12 for burst communication to the transmission line 1. Send to. Therefore, the signal shown in FIG. 11 (a>) is sent to the transmission line 1. On the receiving side, the write control circuit 24 has a signal corresponding to the time slot i/number of the circuit-switched communication area of the received signal frame. Addresses #X2 and #Y2 of areas of the reception buffer 21 where signals X, Y, and Z should be stored.

#Z2 is written, and each received circuit switched signal is stored in a predetermined area of the reception buffer 21.

In this case, the circuit-switched signal Z in the first time slot of the received signal frame is transmitted to the area specified by #Z2, and the circuit-switched signal Y in the third and fourth time slots.

X is stored in areas of the receive buffer 21 given by #Y2 and #X2, respectively. The read control circuit 23 reads out the line-switched values in the receive buffer 21 in time slots 1 to 1 of the bus 200 assigned to each receiving subscriber interface circuit. In this case, the first
Circuit switched signal Z in the second and fourth time slots
, X, and Y are supplied to the bus 200.

On the transmitting side, since the second time slot is vacant (idle), control is started to shift the signal X of the last time slot to this time slot. That is,
The transition control to state iB shown in FIG. 2 is started. First, the second time slot of the transmission frame is used as the circuit-switched signal
The line switching control circuit 10 changes the second area of the readout control circuit 14 from idle to #
, rewrite it as . As a result, as shown in FIG. 11(b), the signal
It is transmitted in duplicate using the th time slot. In this state, the receiving side does not know about the duplicate transmission of signal X, so it performs the same control as in state A. When the line switching control circuit 10 on the transmitting side finishes rewriting the readout control circuit 14, it uses the burst communication area to notify the line switching control circuit on the receiving side that the signal X has shifted to the second time slot. A time slot shift request signal is sent.

When the line switching control circuit 10 (substitute for Fig. 1) on the receiving side receives this, it uses the control signal 10-3 to perform the control circuit 10 (substitute for Fig. 1) as shown in Fig. 3 (b2).
As shown in FIG.
The second area of No. 4 is rewritten from vacant (idle) to #X2 in order to receive signal X. As a result, the signals X of the second and fourth time slots of the received signal frame are written in an overlapping manner in the area given by #X2 of the reception buffer 21. In this case, reading to the bus 200 is performed only once in the period TO, so even if the signal is received redundantly in the receiving buffer 21, it is supplied to the subscriber interface circuit as one circuit switched signal.

Furthermore, the receiving side circuit switching control circuit 10 is configured as shown in FIG. 3 (b3).
As shown in , the fourth area of the read control circuit 24 is rewritten from #X2 to empty (idle). As a result, the line switching signal X in the fourth time slot among the signals shown in FIG. 11(b) is not received by the reception buffer 21.

When this rewriting is completed, the receiving side circuit switching control circuit 1
0 uses the burst communication area to send a response signal back to the transmitting circuit switching control circuit 10. Based on the reception of this response signal, the transmission-Sakaki side line switching control circuit 10 deletes #X1 in the fourth area of the read control circuit 14 of the transmission buffer 11, as shown in FIG. 3(c).
Writes an END signal indicating the end of the circuit switched communication area. As a result, as shown in FIG. 11(c), the circuit switching communication area becomes shorter and the partition from the burst communication area is shifted to the front of the signal frame.

In this embodiment, there is no need to synchronize (time-adjust) the state transition between the transmitting side and the receiving side, so for example, if there is a transmission error in the response signal from the receiving side, can also be recovered using retransmission control. in this case,
The state shown in FIG. 3(b3) only becomes longer, and no problem occurs in the communication of signal X. In this embodiment, if the writing time slot from the transmission buffer 11 to the bus 100 or the reading time slot from the reception buffer 21 to the bus 200 is fixedly allocated to each subscriber, the write control circuit 13. The readout control circuit 23 may use the outputs of the counters 16 and 26 as they are, respectively.

Next, a second embodiment of the present invention will be described with reference to FIG. 11A and FIG. In this embodiment, the transmitting side is the same as the first embodiment, but the receiving side has different functions. On the receiving side, the write control circuit 24 of the receiving buffer 21 has only the function of causing the receiving buffer 21 to receive the signal in the line-switched communication area as it is. Therefore, the receiving buffer 21 has the 11th country (a
) are all received as shown in FIG.
0 No. 1 No. 1'', No. 2 No. 1-1. #Z2, #X2 in the receive buffer 21 in the 4th time slot
．． #Y2te'! j, the circuit-switched signal Z in the area where
Cannot read X and Y. Sending 73 Ilm sends out the signal -X redundantly in the state shown in FIG. 3 (bl), as in the first embodiment. The contents of the reception buffer 21 at this time are shown in FIG. 4 (bl). The receiving side receives the circuit switched signal X from the sending side
Figure 4 (b) based on the time slot shift request fg
Transition to state 2).

lq,'=,, ) That is, #x2 of the read control circuit 23 is rewritten to #X2'. As a result, the second area in the reception buffer 21, that is, the circuit switched signal X given by #X2'
is provided to the subscriber interface circuit as the second time slot signal on bus 200. After this control is completed, the line switching control circuit 10 on the receiving side returns a response signal to the line switching control circuit 10 on the transmitting side. When the transmitting side receives this response signal, it rewrites the contents of the read control circuit 14 and shifts to the state shown in FIG. 4(C).

This situation on the sending side is the same as in the first embodiment.

Next, a third embodiment of the present invention will be described with reference to FIGS. 1 and 5. This embodiment is the same as the first embodiment on the receiving side, but has a different function on the transmitting side. On the transmitting side, as shown in FIG.
Using the th, 5th, and 4th time slots,
The signals are stored in areas designated by #X+, #Y+, and #Z+ of the transmission buffer 11. In this case, this write control organizes the transmission (J" No. 8 frame) in the transmission buffer 11. That is, the signal in the transmission buffer 11 has the structure of the signal frame in the circuit switched communication area shown in FIG. 11(a). The readout control circuit 14 holds the number of time slots of the circuit-switched signal to be transmitted, and in FIG. 5(a), N(-4) is set, and the
The signal shown in Figure (a) is sent out. In this case, when the read control circuit 14 sends out the line switching signals of N time slots, the multiplex control circuit 20 is notified and the partition signal BD is sent out. In the state shown in FIG. 5(bl), on the transmitting side, in order to transmit the circuit switched signal
write to the second area, which is an empty area. Specifically, #x,
'Write. As a result, the outgoing circuit-switched signal
# using the first and second time slots of 0°
They are written in the areas given by X1 and #X1', respectively. Therefore, the signal shown in FIG. 11(b) is sent to the transmission line 1. When the receiving side receives the time slot shift request signal from the transmitting side, it performs the same control as in the first embodiment, and after going through the states shown in FIG. 5(b2) and FIG. 5(b3), responds to the response signal. to be sent back. On the sending side,
When the response signal is received, the write control circuit 13 erases the data of the second #Xl to make it empty as shown in FIG. 5(C). As a result, circuit switched signal X is written to transmission buffer 11 only in the first time slot of bus 100.

In this embodiment, the time slots on the bus 100 on the transmitting side are also shifted in accordance with the time slot shift control on the transmission path 1, but if you want to return the time slots on the bus 100 to their original state, on the transmitting side, #x1' in the second area of the write control circuit 13, which is the position of
, and then empty the first area.

Referring to FIGS. 1 and 6, the fourth embodiment uses the receiving side of the second embodiment and the transmitting side of the third embodiment. That is, the transmission signal frame in the circuit-switched communication area is organized in the transmission buffer 11, and this signal frame is received as is in the reception buffer 21, and the time slot shift control is carried out to the transmission buffer 11 in the same manner as in the third embodiment. This is realized by write control and read control of the reception buffer 21, which is the same as in the second embodiment.

In each of the above embodiments, the circuit switching communication area and the burst communication area are partitioned by the partition signal BD, but instead of this, information giving the length of the circuit switching communication area is provided immediately after the synchronization signal F. It may also be sent as information. In addition, in the configuration shown in FIG. 1, the only component newly added to the communication device in order to implement the present invention is a section that sends partition information every period TO and receives and detects it. Controls the communication function between circuits and the write control circuit and read control circuit of each buffer.
The I function is included as a basic function of a communication device. Therefore,
Time slot shift control is achieved by adding an extremely simple circuit. Regarding burst communication, the period To
Since a partition signal indicating the area is sent for each area, the burst communication area can always be specified even if the partition changes. Additionally, control signals such as time slot request signals and response signals may be sent and received over circuit switched communication areas.

The present invention is applicable not only to one-to-one communication as explained above, but also to
It can be applied to a 1-to-N or even an N-to-N transmission system as shown in FIG. 711g(a) shows a network in which a plurality of nodes 31 to 36 are connected by a loop-shaped transmission line 30, and FIG. 7(b) shows a bus-shaped transmission line 40.
shows a network in which a plurality of nodes 41 to 45 are connected.

FIG. 8 shows the signals on these transmission paths, where the circuit switching signal and the burst communication signal are packetized. here,
The details of the 9 circuit switched code packets (line packets) and burst communication packets (burst packets) are shown in Figure 9 (a> and 9). Figure 9(b) shows that each packet has a start delimiter SD and an end delimiter E.
D, and has a flag C/B indicating whether it is a line packet or a burst. In a line packet, the information field consists of one or more time slots, with an AD giving a unique logical number for this packet. The receiving node receives the circuit switched signal specified by this logical number AD and time slot number. The burst packet has a structure including a destination address DA, a sending address SA as a header, and information INFO. The state of time slot shift control in this case is shown in FIG. 10, FIG. 10(a), FIG. 10(b), and FIG.
) is a state corresponding to FIGS. 11(a) to 11(C). In one-to-one communication, time slot shift control is performed using the synchronization signal F and partition signal BD, whereas in the case of N-to-N communication using line packets, it is simply performed based on the delimiter and logical number AD. In addition, the time slot shift request signal and the response signal may be exchanged with the receiving node communicating using the shifted time slot.

Although a communication system that integrates circuit switched communication and burst communication has been described above as an example, the present invention can also be applied to other communication systems. Multiple circuit-switched signals, specifically,
In a communication system that integrates 64 Kbps and 32 KbpS lines, a 64 KbpS line time slot can accommodate two 32 KbpS line sub-time slots. In this case, depending on the line release state of the 32KbpS line, a plurality of time slots may occur in which only one 32KbpS line can be accommodated.

In this case, by performing time slot shift control according to the present invention, two time slots accommodating only one 32 KbpS line can be combined into one time slot, increasing the number of time slots allocated to the 64 KbpS line. Can be done.

〔Effect of the invention〕

According to the present invention, in a communication system that requires time slot shift control, such as a communication system that integrates circuit switched communication, burst communication, or multiple circuit switched communication, when controlling the time slot shift, a transmitting device and Since there is no need to synchronize the time between receiving devices, control is simplified and a highly reliable communication system that effectively uses signal frames can be provided.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of a communication device using the present invention, and FIG.
The figure shows the control procedure in the present invention, Figure 3 (a) -
Figure 3 (C), Figure 4 (a) to Figure 4 (C), Figure 5 (
a) to FIG. 5(c) and FIG. 6(a) to FIG. 6(C) are the first embodiment of the present invention. 2゜A diagram explaining the third and fourth embodiments, FIG. 7(a) and FIG. 7(b) are diagrams showing another network to which the present invention is applied, and FIG. Figures 9(a), 9(b), and 10(a) show signals on the transmission path in the networks of a) and 7(b).
) to FIG. 10(c) are diagrams showing the configuration of bucket signals used in the networks of FIG. 7(a) and FIG. 7(b), and FIG. 11(a) to FIG. FIG. 12 is a diagram showing a control procedure in a conventional example. 1.2...-Transmission line, 101, 102, 103, 111
．． 112, 113, 201, 202, 203° 211,
212', 213...Subscriber interface circuit, 1
1.12, 21.22...Buffer, 10°13.1
4.15, 20, 23, 24.25...control circuit, 1
6.26...Counter, 17.18...Le 1st
Figure 2 (bt) (C) Chi 3 times (/, /) (b2) Bud 4TM Tea 5 Figure tbf) (shi) Figure 7 (b) $ B Figure 9

Claims (2)

[Claims] (1) In a communication system that performs time slot multiplex communication between a transmitting device and a receiving device, the transmitting device uses a first time slot serving a certain line signal and a second time slot to be shifted. After transmitting the line signal in duplicate, transmitting and receiving a time slot shift request signal that notifies the receiving device of the number information of the line signal whose time slot is to be shifted and the number information of the second time slot to be shifted. The device performs shift control of the reception time slot based on the shift request signal, shifts the reception time slot of the line signal from the first time slot to the second time slot, and then indicates that the shift control has ended. A time slot shift control system characterized in that a response signal is sent to a transmitting device, and the transmitting device that receives the response signal sets only the second time slot as the transmission time slot of the line signal. (2) The transmitting device adds information indicating the length to the signal frame of the time slot multiplex communication and transmits the signal frame, and when the first time slot is the last time slot of the signal frame, the transmitter A time slot preceding the first time slot is given as the time slot of the first time slot, and after receiving the response signal, the first time slot is deleted to shorten the length of the signal frame. The time slot shift control method according to item 1.