JPS6031293B2 - Loop transmission method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a duplex loop transmission system that uses transmission paths efficiently.

With the advancement of online technology, data highways in which a large number of CPUs, terminals, etc. share a high-speed transmission path are now being used in local communication systems due to cost and ease of maintenance.

On the other hand, the data highway also has the disadvantage that a failure in the transmission path immediately leads to system failure. Therefore, it is common for data highways to have duplex transmission paths. In this case, the duplexed transmission line is generally divided into a working line and a protection line, and the working line is normally used, and the protection line is used only when the working line fails. In such a system, when the working line is normal, the protection line is left idle, and considering that there are few occurrences of failures in the transmission line, it cannot be said that the system is used efficiently. SUMMARY OF THE INVENTION An object of the present invention is to provide a duplex loop transmission method that improves the above-mentioned drawbacks, uses transmission paths efficiently, and prevents the system from going down completely even when a failure occurs.

The present invention will be described below with reference to an example of a transmission path having both circuit switching and packet switching functions.

In the system configuration diagram shown in FIG. 1, line 0 and line 1 indicate transmission paths in which the directions of transmission signals are opposite to each other, MS indicates a master station, PX indicates a packet switching slave station, and CX indicates a circuit switching slave station. FIG. 2 is a frame configuration diagram showing the status of identification bits etc. written in the main station MS. In FIG. 2, SY is a synchronization signal insertion location, and the next BI to B5 are identification bit insertion locations, which will be described later, and SY and BI to B5 constitute a control bit CONT. One frame consists of multiple subframes, and the first two bits of each subframe contain an ID for identifying whether the subframe assigned to a circuit switching slave station is a slave station assigned to a packet switching slave station. It consists of bits and a data section into which data is inserted at the slave station. By writing "00" in the BI of the CONT section, it indicates that the line to be connected to group 0 (for example, circuit switching slave station) is 0, and the base is "11".
'' indicates that the line to be followed in group 1 (for example, packet switching slave station) is 1. B
3 indicates that group 0 is instructed to enter the connected state by writing "00", and indicates that group 0 is instructed to leave the line by writing "11", and B4 indicates that group 1 is instructed to leave the line. Indicates the state of B3 in the same way as B3. Furthermore, when only one line is used, B5 instructs a terminal with a lower priority to be temporarily separated from the line by writing "11". Additionally, the data section initially has a slave identification section.

When the master station MS considers the priority level of each slave station as a transmission signal or learns of the presence of communication data by other means, it adds the identification code of that station to the beginning of the data section.
Also, as described above, an identification bit is written and transmitted. When the slave station learns that the subframe can be used by itself,
The partner station is written in the identification section, and data from the own terminal is inserted into the data section and transmitted to the transmission path as will be described later. Third
The figure shows a circuit configuration diagram provided in the main station for writing the above-mentioned bits, lo, 1, to 15 are NAND circuits, 2
o, 2, is an AND circuit, 3 is a line fault detection unit, 4 is an identification bit writing control unit, and 5 is a part that divides the time slot on the highway into one for line switching and one for packet switching when a fault occurs on one line ( CXPX division part). 6o, 6, to 65 are clock signal input terminals, and 7 is a data input terminal.

A time chart of the clock signal is shown in FIG. If there is no information from the line failure detection unit 3 in the write control unit 4, each identification is performed as shown below, for example, the line river is set as a line switched dedicated line for group 0, and line 1 is set as a packet switched dedicated line for group 1. Write bit. Write "00" in BI, "11" in B2, "ooJ" in B3, and "11" in B4 as identification bits for the line 1, and write "00J" in BI, "11" in B2, and "11" in B3 for line 15. "11", B4
Write “00” to and transmit. Therefore, for line 0 as well, output terminals 41, 43 to 45 of write control section 4 are all positive inputs, and 42 is negative input 6. A clock as shown in the time chart of FIG. 4 is added to times 65 to 65. Writing is also performed on the line 1 by controlling the output of the write control section 4 to the same device. Therefore, in this case, in the system shown in FIG. 1, lines 0 and 1 are dedicated to each slave station of the same type as shown in FIG. 5. In Fig. 5, the solid line portion of each slave station indicates that it is connected to the line while data communication is in use, and the broken line portion indicates that it is for inconvenience. 6. In FIG. 6, 8, 82 are receiving devices for each line 0, 1, 9, 92 are line transmission drive devices, 10 is a controller, 11 is a shift register, 12, 1
22 is a JK flip-flop, 13 is a group 0, 1 setting circuit, and 14, 142 is a clock signal input terminal. As shown in the time chart shown in Figure 7. When a lock signal is input, the identification signal that follows the synchronization signal is decoded, and it operates knowing whether to be connected to line 0 or 1. That is, when data is received from line 0, the input data is taken into the shift register 11 by the clock 14. Therefore, 0 and 1 of shift register 1 are bits of B5, 2,
3 is the bit of B4, 4 and 5 are the bits of B3, 6 and 7
The bit of B2 is stored in , and the bit of BI is stored in 8 and 9. These bits 0 to 9 are inputted from each flip-flop to the setting circuit 13 by the clock 142. The setting circuit 13 identifies the bits BI to B5 sent from the main station, determines whether to connect or bypass the line 0', and notifies the control unit 10 of the determination. When the control unit 10 recognizes that it is possible to connect to line 0 according to the setting circuit 13, it identifies the type of slave station that should use the subframe based on the ID bit received following B5, and further When the slave station identification section at the beginning of the data section recognizes that the target station can be used, the data sent from the terminal device via the terminal interface is added to the data section of the received subframe. It is inserted together with identification data and sent to line 0 from driver 9. Further, when line 0 is bypassed, control unit 10 simply passes through the received subframe and sends it to driver 9 and sends it to line 0.

Note that the same applies to line 1. Next, if a fault occurs on one line, the master station detects it and sends a predetermined write to the slave station connected to the faulty line to connect to the other line, as shown in Figure 3. This is performed by the unit 3 and the identification bit write control unit 4.

For example, when line 0 becomes a failure, line 1 is used for CX and PX, so bits BI to B5 are written so that all lines are connected to line 1. And CX, PX
The dividing unit 5 divides each subframe into respective CX and PX
Assign to. The subframes to be allocated to the CX and PX are set in advance when starting up the system.Then, the CXPX division unit 5 uses the information from the failure detection unit 3 to assign each subframe after B5. Write "00" and "11" according to the subframe configuration set in the ID bit. At this time, for example, for CX and PX with low priority, the B5 bit is set to "
11", bypass the CX and PX with lower priority, wait for line 0 to be restored, and then write this C
Connect X to line 0 and PX to line 1.

Then, the control section 10 of each slave station identifies the subframe to be used by the target station based on the information from the setting circuit 13, the information on the ID bit, and the information on the slave station identification section at the head of the data section. In this way, according to the present invention, if both duplicated transmission lines are normal, it is possible to use both to increase communication capacity, and if a failure occurs in either one, communication can be performed using only the normal one. The transmission path can be used efficiently.

[Brief explanation of the drawing]

Fig. 1 is a system configuration diagram according to an embodiment of the present invention, Fig. 2 is an identification signal explanatory diagram, Fig. 3 is a main station write circuit configuration diagram, Fig. 4 is an operation explanatory diagram of Fig. 3, and Fig. 5 is an explanatory diagram of the writing circuit of the main station. Line usage diagram,
FIG. 6 is a block diagram of the slave station device, and FIG. 7 is an explanatory diagram of the operation of FIG. 6. Figure 1: Tsukanozu, Figure 4, Figure 5, Figure 3, Figure 6, Sei 7

Claims (1)

[Claims] 1 In a system that performs loop transmission by providing a duplex transmission line between a master station and multiple slave stations, each slave station is divided into one for line switching and one for packet switching, and both systems of the duplex transmission line are normal. In such cases, communication is performed by connecting a line-switching slave station to one transmission line and a packet-switching slave station to the other transmission line. If either transmission line fails, the slave station and the master station A loop transmission method characterized by detecting at a station, dividing one frame into a plurality of subframes, and transmitting the frame as a mixture of circuit switching subframes and packet switching subframes.