JP3331399B2 - Local area network - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a local area network (LAN), and more particularly to an improvement in a clock synchronization system.

[0002]

2. Description of the Related Art In a conventional loop-type local area network, a master clock is generated at a specific node, and the other nodes adopt a subordinate synchronization system in which synchronization is performed by the master clock.

[0003]

The object of the invention is to be Solved However, such Lumpur
When adopting the frame synchronization method in the case of a loop- type local area network, the total length of the loop needs to be an integral multiple of the frame. Therefore, it is necessary to perform frame synchronization at a specific node so as to absorb the phase difference between the independent transmission timing and the reception timing extracted from the received data.

The present invention has been made to solve such a conventional problem. A clock generator is provided in each of the interface units of a line, and an independent synchronization system using this clock is used to reduce the system downtime. Local area net that can avoid fatal problems such as
Another object of the present invention is to provide a local area network capable of transmitting packets with a delay as short as possible in the case of packet communication. It is another object of the present invention to provide a local area network capable of reliably performing clock synchronization with another interface.

[0005]

In a local area network according to a first aspect of the present invention, a plurality of data devices are respectively connected to a transmission line in a loop type via an interface unit, and each interface includes a clock generator. Prepared,
In a local area network that is independently synchronized by destuff / stuff, the transmission path performs packet communication, and each interface section runs by itself.
Read counter and the count of the read counter
A packet to which a received packet is written with the value as the read address
Buffer and the timing signal in the header of the received packet.
Loads a predetermined value into itself as a load signal,
The address of the buffer corresponding to the count value
A write counter for writing a packet.
A timing at which the predetermined value is loaded into the
The read to the value loaded in the write counter
The difference from the timing at which the counter value reaches the delay time
The automatic delay adjustment of the packet is performed.

[0006]

A local area network according to a second invention is the local area network according to the first invention, wherein data amount detection means for detecting an amount of data input to each interface unit ;
Clock generating means for generating a clock in accordance with the data amount detected by the data amount detecting means;
The interface unit is operated by a clock generated by the generating unit .

According to a third aspect of the present invention, in the local area network according to the first aspect , the transmission path is N-multiplexed, and a part of the interface unit on the transmission path side is N-multiplexed.
The multiplexed transmission line is connected to an interface unit for use as a multi-route, and means for monitoring the amount of data from each transmission line, and a unit for maximizing the amount of data within a predetermined time. Means for generating a clock based on the clock, and operating each interface unit by the clock.

[0009]

According to the first aspect of the present invention, the write counter
Timing when the read counter reaches the value
Independent synchronization method that automatically adjusts the packet delay using the difference of the delay time as the delay time, so that even if a failure occurs in one of the interface units, it does not spread to the other and the system down can be avoided, Packet communication can be performed without restriction on the transmission path length, and the time delay can be shortened as much as possible.

According to a second aspect of the present invention, in the first aspect, the interface unit can be operated with a synchronous clock in accordance with the received data, and even when a public network is connected, the interface unit can be operated in synchronization with the public network. It is easily possible. In the third invention, the first invention
When the transmission path is multiplexed, the clock is generated based on the most reliable received data, so that the accuracy of the clock is improved.

[0011]

FIG. 1 is a system structural diagram of a local area network according to the present invention, and FIG. 2 is a block diagram of an interface unit. Transmission line A is multiplexed. Interface sections C to H are connected to a plurality of transmission paths A made of optical fibers in a loop type. Each interface unit is connected to a host computer (not shown), a data device such as a terminal K, or an exchange B connected to a public network.

Reference numeral 2 denotes an optical interface unit which is duplexed on both the receiving side on the left side and the transmitting side on the right side in FIG. First, regarding the receiving side, 2 of transmission path A
The book is connected to the optical / electrical conversion units 201, 201, converts the received optical signals into electric signals, and inputs the electric signals to the selector 203.
Optical / electrical converters 201, 201 are various alarms for received data
(Light interruption, etc.) is detected and given to the selection control unit 202. Based on this, the selection control unit 202 issues a control signal to the selector 203 to selectively output one of the two inputs to the packet processing unit 3.

The output of the selector 203 is supplied to a clock transfer unit 301.
Then, the received data (based on the clock of the transmission path) is replaced with the clock generated by the internal clock generator 302, and the data is destuffed and synchronized. The clock output from the clock generator 302 is also used as a master clock of this interface unit. Therefore, the clock continues to be generated even when reception is stopped.

The received data after the clock change is input to the received packet processing unit 303, where the header of the received packet is examined, and the reception / relay determination is performed. When relaying a packet, the packet is sent to the repeat unit 304, and the received packet is buffered here. Then, this is relayed and transmitted in synchronization with a signal received from the packet transmitting unit 305 at the timing of a packet header on the transmitting side described later.

The received packet is input to reception arbitration units 307, 307,... The reception arbitration units 307, 307 contain a large number of line set units 4, 4,..., But do not directly perform reception arbitration, but first perform arbitration between the reception arbitration units 307, 307, and I do.

The line set unit 4 selects multiplexed data. Similarly, for the transmission lines other than the two transmission lines connected to the optical / electrical conversion units 201, 201 shown in FIG. The data from the reception arbitration unit 307 is input via the unit 3. The received packet is first sent to the line set changing unit 401 by the line clock changing unit 401.
Clock. This clock is created by the master clock.

The received packet is also transmitted to a received packet processing unit 40.
It is input to 2 and checks the sequence number and source address from the header information of the received packet, checks the CRC, etc., and discards the packet. The number of received packets is counted for each route, and PLL is performed according to the data amount.

A multiplexing selection unit 403 selects multiplexed reception data, and a reception packet processing unit 402
The status of the received data is indicated by a flag according to the processing result in step (1). The multiplexing select is performed by writing data in accordance with the sequence number, absorbing the phase difference of the received data via each route, and reading the normal data while checking the status of the data of the same phase with the flag.

FIG. 3 is a block diagram of a main part of the line set section 4, showing a doubled one. Each of the received packet processing units 402 includes a source check unit 402a that receives a received packet and detects a source address, a CRC check unit 402b that performs a CRC check, and a latch unit 402c that recognizes a sequence number from header information.

The received packet is input to a FIFO memory 401a and a data amount detection unit 401b which constitute the clock transfer unit 401. The data amount detection unit 401b detects the amount of received data,
Clock generation circuit 401 using a PLL or the like according to the detection amount
Control c. The function of the data amount detection unit 401b is to count the number of received packets for a certain period, and control the clock generation circuit 401c to keep this count value at a certain value.

As shown in the figure, the received packet is input from the multiplexed transmission path, but the data amount detection unit 401b determines that the data of the transmission path that has received a large number of data in a predetermined time is correct, thereby generating a clock. The circuit 401c is controlled.
Such clock control depends on transmitted data, but a line clock is used in an interface unit to which a main line is allocated as described later.

The output of the clock generation circuit 401c is used as the clock LSCLK of the line set unit 4. This clock is provided to the FIFO memory 401a, which allows the clock to be switched. When the detected transmission source is not defined, the transmission source check unit 402a discards the contents of the FIFO memory 401a, that is, the received packet. CRC check section 40
When a CRC error is detected by 2b, data is written to the reception buffer 403c constituting the multiplex selection unit 403, but the flag control unit 403a constituting the multiplex selection unit 403 is written.
Do not set.

When there is no CRC error, the reception buffer 40
Data is written to 3c, and a flag of the flag control unit 403a corresponding to the sequence number of the received packet is set. The latch contents of the latch section 402c for latching the sequence number are written in the write control section 40 constituting the multiplexing select section 403.
3b, and is written to the address of the reception buffer 403c predetermined by each number.

Reference numeral 403d denotes a read buffer read control unit, which starts reading data from the receive buffer 403c when the amount of received data reaches a predetermined value. This outputs normal data to the terminal K or the like via the selection circuit 403e while checking the flag based on the sequence number that has started receiving. Here, when both of the duplicated packets from both systems are not normal values, this is reported to the outside.

5 is a line set (LS) switch unit,
The multiplexed line set unit 4 is selected by the selection unit 501. The selection control is performed by the select control unit 502, which receives a status flag corresponding to the data from the line set unit 4 and selects a line set for transmitting normal data. The received data selected in this way is sent to the terminal K. In FIG. 1, reference numeral 6 denotes a multiplexer for sharing one line set unit 4 with a plurality of terminals K, K.

Next, regarding the transmitting side, the data given from the terminal K is input to the transmission control unit 404 of the multiplexed line set unit 4 via the transmission unit 503 of the LS switch unit 5. The transmission control unit 404 packetizes the input data and sends the packetized data to a plurality of packet processing units 3 via transmission buffers 405, 405.
To the transmission arbitration unit 308.

The transmission arbitration units 308, 308...
, And then arbitrates between the transmission arbitration units 308, 308, and sends out a packet with a transmission permission signal generated by the arbitration unit. The packet transmitting unit 305 gives the timing of the header to the repeat unit 304 for transmitting the relay packet, and passes the packet to the multiplexing unit 306. The multiplexing unit 306 adds a stuff or the like to a packet of data to be transmitted and multiplexes it into a frame on the transmission path A.
The optical signal is transmitted from the electrical / optical converters 205 and 205 to the transmission path A via the optical signal. The repeat processing unit 304 buffers the packet to be relayed as described above, but automatically adjusts the delay by relaying the packet at the timing of the packet header on the transmission side.

FIG. 4 is an explanatory diagram of the automatic delay adjustment in the repeat processing section 304. FIG. 5 shows an example in which the number of interface units is four, ie,,,, and SHD1, SHD2,..., SHD4 indicate the timing of the header of the transmission packet in each of the four interface units,. , RHD1, RHD2,..., RHD4 indicate the timing of the header of each of the four interface units,.

P, Q, R, S, and T represent packets. The packet is sent to the interface,
Are sent in this order. The packet transmitted from the interface unit is received by the interface unit on the transmission path with a delay of time t ₁ , and the repeat processing unit
Only T ₂ is delayed by 304. Then, the signal is transmitted to the next interface unit with a delay t ₂ in the transmission path. Similarly, each node transmits packets with delays of T ₃ , T ₄ , and T ₁ .

Focusing now on the interface section, the header of the received packet is detected at the timing of A. The repeat processing unit 304 can perform automatic adjustment by delaying the timing of the header of the transmission packet so as to match the transmission end timing of the previous packet. Although the symbols P, Q, R, S, and T of the transmission packet shown in FIG. 4 are not changed at all, it is needless to say that the symbols are only for indicating the timing, and the same packet does not circulate.

By performing such transmission, the transmission path length of the loop can be reduced to a minimum packet fraction of one packet or more (two packets in the illustrated example), and a packet is inserted into this transmission path. You can do it. In other words, since reception and transmission are independent in the stuff synchronization method, if this is applied to a loop-type local area network, even if synchronization can be established, since there is only a delay in the transmission path length, one interface From the viewpoint of the section, the transmission path may not be able to secure the minimum unit of communication (one packet).

However, in the present invention, the delay adjustment function
Due to its presence, apparently more than one packet can be inserted
The transmission path length can be secured. Also such an interface
-The delay time t on the transmission line₁What kind of
Even if it is a value, it determines the buffer time inside itself and automatically
Delay in the system construction ₁
No measurement is required. In addition, the interface considering it
There is no need to adjust the ace itself.

FIG. 6 is a block diagram showing a main part of the repeat processing unit 304. The buffer 304a for writing the received packet uses the count value of the self-running read counter 304b as the read address, and this count value is decoded by the decoder 304c, and the decoded signal is the timing signal SH of the transmission header.
It is used as a D. On the other hand, the write counter 304d outputs the timing signal RHD of the header of the received packet as a load signal.
(LOAD) being adapted to load a predetermined value in itself as also thereby writes the received packet counter
Write to the address of the buffer 304a corresponding to the count value of 304d. That is, a predetermined value is loaded into the write counter 304d.
And the timing that, load of this writing counter 304d
The difference between the count value reaches the timing of the read counter 304b for self-propelled in the value is of the delay time.

FIG. 7 is a block diagram showing a case of duplexing as an example to make it easier to understand how the interface section is multiplexed. Therefore, the transmission path A is also duplicated, and this is used as two routes. The optical transmission line A ₁ (A ₂ ) is connected to the optical interface unit 2 ₁ (2 ₂ ),
A packet processing unit 3 ₁ (3 ₂ ) is connected to the optical interface unit 2 ₁ (2 ₂ ).
7 ₁ , (307 ₂ ) and transmission arbitration units 308 ₁ , (308 ₂ ) are connected to a line set unit 4 common to two systems, and a terminal K is connected to the line set unit 4.

The difference between FIG. 7 and FIG. 2 is the configuration of the optical interface unit. In the configuration of FIG. 2, the optical / electric conversion unit and the electric / optical conversion unit are duplicated to provide a redundant configuration.
FIG. 7 does not show such a redundant configuration. If by construction as shown in FIG. 7 gives the correct one to judge the normality / abnormality of the two data received via the transmission line A ₁ and / or A ₂ in the line setting section 4 to the terminal K.

Therefore, even if a failure occurs in _{one of} the transmission lines A ₁ and A ₂ , the optical interface units 2 ₁ and 2 ₂ , and the packet processing units 3 ₁ and 3 ₂ , the data can be switched and received substantially instantaneously without interruption. It is possible.

On the other hand, the transmission system will be described. The data leaving the terminal K passes through a line set unit 4 to a packet processing unit 3 ₁ ,
3 ₂ reaches the, where it is packetized gradually sent out from the optical interface unit 2 _1, 2 ₂ to the transmission line A _1, A _2. If the transmission is normally performed on two routes, the data on the normal side will be received even if some trouble occurs on one of the data routes on the receiving side as described above. Since the transmission system is duplicated, even if a failure occurs in one of the transmission systems, normal data reception is ensured as long as there is no failure on the receiving side.

Returning to FIG. 1, the operation of this system will be described. For example, a line connecting the interface unit C and the exchange B (for example, connected to a public network) is defined as a main line, and a line connecting the other interface units (D to H) and the terminal is defined as a slave line. One of 101
Is defined as a spare main line.

In the interface section C connected to the main line, a packet is transmitted using the clock from the main line 100 as a master. The other interface units (D to H) control the clock according to this packet as described above. If an accident occurs on the main line 100, the slave line 10
When the LS switch unit 5 of the interface unit H connected to 1 detects this, the communication is enabled between the units except for the interface unit C by setting this to the main line mode.

[0040]

As described above, according to the present invention, it is possible to construct a highly reliable network that does not lead to a system down due to a clock trouble.
In addition, a network can be realized in which there is little restriction on the length of the transmission path and packet communication can be performed efficiently with a short delay time. Further, since the clock is generated in accordance with the amount of received data, clock synchronization with other interfaces, and further with a public network connected through the other interfaces, can be ensured. Further, when the transmission paths are multiplexed, the reliability is further increased by generating a clock according to the data having the highest reliability.

[Brief description of the drawings]

FIG. 1 is a system configuration diagram of the present invention.

FIG. 2 is a block diagram of an interface unit.

FIG. 3 is a block diagram of a line set unit.

FIG. 4 is an explanatory diagram of automatic delay adjustment.

FIG. 5 is an explanatory diagram of automatic delay adjustment.

FIG. 6 is a block diagram of a repeat processing unit.

FIG. 7 is a block diagram of a duplex interface unit.

[Explanation of symbols]

A, A _1, A ₂ transmission lines C, D, E, F, G, H ,,,, interface unit 2, 2 _1, 2 ₂ optical interface unit 3, 3 _1, 3 ₂ packet processor 4 line-set portion

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-61-206345 (JP, A) JP-A-63-266940 (JP, A) JP-A-2-86348 (JP, A) JP-A 62-86348 13142 (JP, A) JP-A-62-72251 (JP, A) JP-A-61-270937 (JP, A) JP-A-61-23449 (JP, A) (58) Fields investigated (Int. ⁷ , DB name) H04L 12/42

Claims (3)

(57) [Claims] 1. A plurality of data devices are connected to a transmission line in a loop type via an interface unit. Each interface is provided with a clock generator, and is independently synchronized by destuff / stuff. In a local area network, a transmission path performs packet communication, and each interface receives a self-running read counter and a count value of the read counter as a read address.
The buffer into which the received packet is written, and the timing signal of the header of the received packet as the load signal
And load a predetermined value into itself, and count value from this predetermined value
Write the received packet to the address of the buffer corresponding to
A write counter for writing, tie the predetermined value is loaded into the write counter
And the value loaded into the write counter
Difference from the timing at which the count value of the read / write counter reaches
A local area network characterized in that automatic delay adjustment of a packet is performed using the delay time as a delay time . 2. A data amount detecting means for detecting an amount of data input to each interface unit, and detecting the data amount.
Means for generating a clock according to the amount of data detected by the means .
Lock generation means, wherein the clock generation means
The local area network according to claim 1, wherein the interface unit is operated by a clock . Wherein said transmission line is N-multiplex, also a part of the transmission line side of the interface unit are N multiplexed transmission path multiplexed by connecting to the interface unit to be used as a multi-route There is a means for monitoring the amount of data from each transmission path, and a means for generating a clock based on the one with the largest amount of data within a predetermined time,
The local area network according to claim 1, wherein each interface unit is operated by the clock.