JPH05160845A - Local area network - Google Patents

Abstract

PURPOSE:To obtain the local area network in which the transmission of erroneous data is prevented and a disadvantage of sharing of a specific line over a transmission line for a long time is avoided. CONSTITUTION:Plural lines are connected to transmission lines A, A1, A2 via interface sections C-H respectively. Each of the interface sections C-H is provided with a means discriminating whether or not a reception data is sent from a predetermined line and a means invalidating the reception data when the result of discrimination of the means indicates negative discrimination.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a local area network (LAN), and more particularly, to prevent transmission of abnormal data or to prevent a specific line from occupying a transmission line for a long period of time. Related to the local area network.

[0002]

2. Description of the Related Art When packet communication is performed, if there is an abnormality in a packet header, this abnormality will be detected only after being analyzed in an upper layer. Therefore, packets are transmitted until then and useless communication is performed. Further, this abnormal data may cause a system malfunction or, in the worst case, cause the system to go down. Further, a specific line has been able to occupy the entire transmission line in order to transmit a large amount of data, but this causes a problem that other communication cannot be performed.

The present invention has been made in order to solve the problem of such a conventional local area network, invalidates the received data from an undefined line, and masks the transmitted data in a quantity larger than a specified amount. It is therefore an object of the present invention to provide a local area network in which unnecessary data communication is not performed, the system is operated safely, and further, some line transmission paths are not occupied for a long period of time.

[0004]

A local area network according to a first aspect of the present invention is a local area network in which a plurality of lines are connected to a transmission line via respective interface sections, wherein the interface section is configured to receive data. Is provided with a means for determining whether or not the transmission is from a pre-defined line, and means for invalidating the received data when the determination result of the means is negative.

A local area network according to a second aspect of the present invention is a local area network in which a plurality of lines are connected to a transmission line via respective interface units, and means for monitoring the amount of data transmitted from the interface units. And a means for masking the transmission when the transmission data amount is larger than a prescribed amount.

[0006]

[Operation] Since the received data from the undefined source is an abnormal header, by invalidating it,
It is possible to prevent the failure of the interface unit related to the transmission of the header abnormal packet from spreading. Further, since the abnormal reception data is detected by the interface unit, useless communication can be stopped early. Further, when the amount of data to be transmitted is equal to or more than the specified amount, the transmission is masked, so that the transmission line is not occupied by the transmission line for a long time.

[0007]

1 is a system structure diagram of a local area network of the present invention, and FIG. 2 is a block diagram of an interface section. The transmission line A is multiplexed. A plurality of transmission lines A made of optical fibers are connected to the interface unit C of the line.
~ H are connected in a loop. A host computer (not shown), a data device such as a terminal K, or an exchange B connected to a public network is connected to each of the interface units C to H.

Reference numeral 2 denotes an optical interface section, which is duplicated on both the receiving side on the left side and the transmitting side on the right side in FIG. First, looking at the receiving side, 2 of transmission line A
The book is connected to the optical / electrical conversion units 201, 201, and converts the received optical signal into an electric signal and inputs it to the selector 203.
Optical / electrical converters 201, 201 are various alarms for received data
(Light interruption, etc.) is detected and given to the selection control unit 202. Based on this, the selection control unit 202 issues a control signal to the selector 203 to selectively output one of the two inputs to the packet processing unit 3.

The output of the selector 203 is the clock transfer unit 301.
The received data (according to the clock of the transmission path) is transferred to the clock generated by the internal clock generator 302, and destuffing is performed for synchronization. The clock output from the clock generator 302 is also used as the master clock of this interface section. Therefore, the clock continues to be emitted even when reception is interrupted.

The received data whose clocks have been changed is input to the received packet processing unit 303, where the header of the received packet is examined, and reception / relay determination is performed. When the packet is relayed, it is sent to the repeat processing unit 304, and the received packet is buffered here. Then, at the timing of the packet header on the transmitting side, which will be described later,
This is relayed in synchronization with the signal received from 5.

The received packet is input to the reception arbitration units 307, 307 .... In the case of a large-scale configuration, a large number of line set units 4, 4, ... Are accommodated, but the reception arbitration units 307, 307 ... Do not perform direct reception arbitration, but first perform arbitration between the reception arbitration units 307, 307. The reception arbitration of the unit 4 is performed.

The line set unit 4 is for selecting multiplexed data, and the transmission line other than the two transmission lines connected to the optical / electrical conversion units 201, 201 shown in the figure similarly uses the optical interface unit 2 and packet processing. The data from the reception arbitration unit 307 is input via the unit 3. First, the received packet is sent by the line clock transfer unit 401 to the line set unit 4
Can be transferred to the clock. This clock is created by the master clock.

The received packet is also processed by the received packet processing unit 40.
It is input to 2 and confirms the sequence number and source address and CRC check from the header information of the received packet, and discards the packet. In addition, the number of received packets is counted for each route, and PLL is performed according to the amount of data.

The multiplexing selection section 403 selects the multiplexed reception data, and the reception packet processing section 402
The state of the received data is displayed as a flag according to the processing result in (1). In addition, data is written here according to the sequence number to absorb the phase difference of the received data via each route, and normal data is read while observing the flag of the data of the same phase to perform multiplexed selection.

FIG. 3 is a block diagram of a main part of the line set unit 4 on the receiving side, showing a duplicated one. Each of the received packet processing units 402 detects the source address when the received packet is input to the source check unit 402a, CRC
A CRC check unit 402b for checking and a latch unit 402c for recognizing a sequence number from header information.

The received packet is input to the FIFO memory 401a and the data amount detection unit 401b which form the clock transfer unit 401. The data amount detection unit 401b detects the received data amount,
Clock generation circuit 401 that uses PLL etc. according to the detection amount
Control c. The function of the data amount detection unit 401b is to count the number of received packets for a certain period of time and control the clock generation circuit 401c so that this count value becomes a certain value.

As shown in the figure, the received packet is input from the multiplexed transmission line, but the data amount detection unit 401b determines that the data on the transmission line that has received a large amount of data at a predetermined time is correct, and the clock is generated accordingly. It controls the circuit 401c.
Such clock control depends on the data to be transmitted, but the line clock is used in the interface section to which the main line is allocated as described later.

The output of the clock generation circuit 401c is used as the clock LSCLK of the line set section 4. This clock is given to the FIFO memory 401a, which makes it possible to change the clock. The transmission source check unit 402a determines whether or not the detected transmission source is defined, and if it is not defined, the contents of the FIFO memory 401a, that is, the received packet is discarded. When a CRC error is detected by the CRC check unit 402b, the data is written in the reception buffer 403c that constitutes the multiplex selection unit 403.
The flag control unit 403a constituting 403 is not set.

When there is no CRC error, the receive buffer 40
Data is written to 3c and the flag corresponding to the sequence number of the received packet is set by the flag control unit 403a. The latch content of the latch unit 402c that latches the sequence number is the write control unit 40 that constitutes the multiplex select unit 403.
It is given to 3b and written in the address of the reception buffer 403c which is predetermined by each number.

Reference numeral 403d is a read buffer read control unit, which starts reading data from the receive buffer 403c when the amount of received data reaches a predetermined value. This outputs normal data to the terminal K or the like via the selection circuit 403e while confirming the flag according to the sequence number at which reception is started. If the packets from both systems duplicated here are not normal values, this is notified to the outside.

Reference numeral 5 is a line set (LS) switch section,
The select line 501 selects the multiplexed line set unit 4. The selection control is performed by the selection control unit 502, which receives a status flag corresponding to the data from the line setting unit 4 and selects the line set to which normal data is transmitted. The reception data selected in this way is sent to the terminal K. Reference numeral 6 in FIG. 1 is a multiplexing device for sharing one line setting unit 4 by a plurality of terminals K, K ...

Next, looking at the transmitting side, the data given from the terminal K is inputted to the transmission control section 404 of the multiplexed line setting section 4 via the transmitting section 503 of the LS switch section 5. The transmission control unit 404 packetizes the input data and transmits a plurality of packet processing units 3 via the transmission buffers 405, 405.
To the transmission arbitration unit 308.

The transmission arbitration units 308, 308 ... Are line set units 4.
After the transmission arbitration is performed, the transmission arbitration units 308, 308 ... The packet transmission unit 305 gives the timing of the header to the repeat unit 304 for transmitting the relay packet, while passing the packet to the multiplexing unit 306. The multiplexing unit 306 adds stuff or the like to the packet of data to be transmitted and multiplexes it into the frame on the transmission path A, and the transmission unit 204 of the optical interface unit 2
An optical signal is sent from the electric / optical conversion units 205, 205 to the transmission line A via the. The repeat processing unit 304 buffers the packet to be relayed as described above, but automatically repeats the delay by relaying the packet at the timing of the packet header on the transmitting side.

FIG. 4 is a block diagram of the main part of the line set section on the transmission side, showing the details of the transmission control section 404. The transmission data packetized by a portion (not shown) of the transmission control unit is the write clock WCLK and the effective data area signal TIM1.
Is written to the send buffer 405 by. Transmission control circuit
404a issues a transmission request signal to the transmission arbitration unit 308, and when transmission is permitted, returns an "H" level transmission permission signal to the AND gate 404b. The data amount is added to the header part of the transmission packet, but the transmission abnormality detection part 404c checks this and if it is larger than the specified value, it is sent to the AND gate 404b.
Input "L" level signal. Conversely if it is small
Input "H" level signal.

When the output of the AND gate 404b becomes "H" level, the read clock RCLK is given to the transmission buffer 405 via the AND gate 404d to output it. The output of this transmission buffer 405 is the data from the transmission header table 404e which stores other header information and the multiplexer 404f.
Are combined and given to the packet processing unit 3.

FIG. 5 is an explanatory diagram of automatic delay adjustment in the repeat processing section 304. As shown in FIG. 6, there is shown an example in the case where there are four interface parts, and SHD1, SHD2 ... SHD4 indicate the timing of the header of the transmission packet in each of the four interface parts. , RHD1, RHD2 ... RHD4 indicate the timings of the headers of the respective received packets of the four interface units.

Further, P, Q, R, S and T represent packets. The packet is the interface part ...
Are sent in the order of. The packet transmitted from the interface unit is received by the interface unit with a delay of time t _{1 on the} transmission path, and the repeat processing unit here.
Delay at T ₂ by T ₂ . Then, it is transmitted to the next interface unit with a delay t ₂ on the transmission path. Similarly, packets are transmitted at each node with a delay of T ₃ , T ₄ , and T ₁ .

Now, paying attention to the interface section, the header of the received packet is detected at the timing a. The repeat processing unit 304 can perform automatic adjustment by delaying the timing of the header of the transmission packet so as to match the transmission end timing of the previous packet. The symbols P, Q, R, S, T of the transmission packet shown in FIG. 5 are not changed at all, but it is a symbol only showing the timing, and it goes without saying that the same packet does not circulate.

By performing such transmission, the transmission line length of the loop can be shortened to the minimum packet fraction of one packet or more (two packets in the illustrated example), and the packet is inserted into this transmission line. You can do it. In other words, in the stuff synchronization method, reception and transmission are independent, so if this is applied to a loop-type local area network, even if synchronization can be established, the length of the transmission path is only a delay, so there is only one interface. From the perspective of the parts, it may happen that the transmission path cannot secure the minimum unit of communication (1 packet).

However, in this embodiment, the presence of the delay adjusting function makes it possible to secure an apparent transmission path length capable of inserting one packet or more. Since such an interface unit causes the automatic delay defines a buffer time within its own delay be time t ₁ what value the like in the transmission path, the measurement of such delay times t ₁ When constructing systems Is unnecessary. Further, it is not necessary to adjust the interface unit itself in consideration of it.

FIG. 7 is a block diagram showing the main part of the repeat processing section 304. The buffer 304a for writing the received packet uses the count value of the free-running read counter 304b as a read address, this count value is decoded by the decoder 304c, and the decoded signal is the timing signal SHD of the transmission header.
On the other hand, the write counter 304d is designed to load a predetermined value to the timing signal RHD of the header of the received packet as a load signal (LOAD). Write the received packet to the address corresponding to. That is, the difference between the timing of loading to the counter 304d and the timing of reaching the loaded value by the free-running counter 304b is the delay time.

FIG. 8 is a block diagram showing an example of duplication in order to make it easier to understand how the interface unit is multiplexed. Therefore, the transmission line A is also duplicated and used as two routes. The optical transmission line A ₁ (A ₂ ) is connected to the optical interface unit 2 ₁ (2 ₂ ),
A packet processing unit 3 ₁ (3 ₂ ) is connected to the optical interface unit 2 ₁ (2 ₂ ) and its reception arbitration unit 30
7 ₁ , (307 ₂ ) and the transmission arbitration unit 308 ₁ , (308 ₂ ) are connected to the line set unit 4 common to the two systems, and the terminal K is connected to the line set unit 4.

The difference between FIG. 8 and FIG. 2 is the configuration of the optical interface section. In the configuration of FIG. 2, the optical / electrical conversion section and the electrical / optical conversion section are duplicated to form a redundant configuration.
In FIG. 8, such a redundant configuration is not used. In the case of the configuration as shown in FIG. 8, the line set unit 4 judges whether the two data received via the transmission lines A ₁ and / or A ₂ are normal or abnormal and gives the correct one to the terminal K.

Therefore, even if a failure occurs in _{one of} the transmission lines A ₁ and A ₂ , the optical interface units 2 ₁ and 2 ₂ and the packet processing units 3 ₁ and 3 ₂ , data can be switched and received substantially without interruption. It is possible.

On the other hand, let us consider the transmission system. The data output from the terminal K passes through the line set unit 4 and the packet processing unit 3 ₁ .
3 ₂ reaches the, where it is packetized gradually sent out from the optical interface unit 2 _1, 2 ₂ to the transmission line A _1, A _2. When the data is normally transmitted by two routes, the receiving side receives the normal data even if some failure occurs in one data route as described above. Since the transmission system is duplicated, even if a failure occurs in one of them, normal data reception is ensured as long as there is no failure on the receiving side.

Returning to FIG. 1 again, the operating mode of this system will be described. For example, a line connecting the interface unit C and the exchange B (for example, connected to the public network) is defined as a main line, and a line connecting the other interface units (D to H) and the terminal is defined as a slave line. One of 101
Is defined as a spare main line.

In the interface section C connected to the main line, the clock from the main line 100 is used as a master to send the packet. As described above, the clock is controlled according to this packet in the other interface units (D to H). If an accident occurs on the main line 100, the sub line 10
When the LS switch section 5 of the interface section H connected to 1 detects this, it sets this as the main line mode and enables communication between the sections except the interface section C.

[0038]

According to the present invention as described above, when an abnormality occurs in data indicating the transmission source of the packet header portion due to a failure in any of the interface portions, this is promptly detected by the interface portion. It is possible to prevent unnecessary communication. In addition, it is possible to avoid the inconvenience that the influence of the failure is propagated to other interface units and the system goes down. Further, since the data exceeding the specified amount is not transmitted, there is no inconvenience that a transmission line is occupied by a specific line for a long time.

[Brief description of drawings]

FIG. 1 is a system configuration diagram of the present invention.

FIG. 2 is a block diagram of an interface unit.

FIG. 3 is a block diagram of a line setting unit.

FIG. 4 is a block diagram of a line setting unit.

FIG. 5 is an explanatory diagram of automatic delay adjustment.

FIG. 6 is an explanatory diagram of automatic delay adjustment.

FIG. 7 is a block diagram of a repeat processing unit.

FIG. 8 is a block diagram of a duplex interface unit.

[Explanation of symbols]

A, A ₁ , A ₂ Transmission path C, D, E, F, G, H, ..., Interface section 2, 2 ₁ , 2 ₂ Optical interface section 3, 3 ₁ , 3 ₂ Packet processing section 4 Line setting section 402 Received packet processing unit 402a Source check unit 404 Transmission control unit 404b AND gate 404c Transmission error detection unit

Claims (2)

[Claims] _{1. In} a local area network in which a plurality of lines are connected to transmission lines (A, A ₁ , A ₂ ) via interface units (C to H), the interface units (C to H) are provided. Is means for determining whether or not the received data is transmitted from a predefined line
A local area network comprising: (402a); and means (402a) for invalidating received data when the determination result of the means is negative. 2. In a local area network in which a plurality of lines are connected to transmission lines (A, A ₁ , A ₂ ) via interface units (C to H), the interface units (C to H) are provided. A local area network comprising means (404c) for monitoring the amount of transmission data from the device, and means (404c, 404b) for masking the transmission when the amount of transmission data is larger than a prescribed amount.