JP2663624B2 - Instantaneous interruption switching method of redundant circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] Regarding the switching system of the duplex circuit provided corresponding to the duplex data bus, always keep the normal D data even at the time of N / E switching of the bus. Check bits inserted into digital data by an error detection unit that detects an error in the output of a disconnection / error detection unit or data processing unit in a normal circuit with the objective of providing a double-stop circuit for instantaneous interruption switching of output. Has detected an error,
Also when switching to the emergency circuit under the control of the N / E switching control circuit, the digital data held in the holding means is read by the data reading means and sent to the terminal or the transmission line via the output bus buffer unit. It is configured so that:

[Industrial applications]

The present invention relates to a switching system for a redundant circuit provided corresponding to a redundant data bus.

A composite synchronous multiplexing device, which is a device used for synchronizing and multiplexing and transmitting multiplexed data (including a clock) of image, voice, information, and the like, includes a time slot conversion shelf and a terminal or transmission line interface. And a face shell.

In addition, a shelf refers to a group of shelves on which devices in which a certain number of devices of the same type are mounted vertically or horizontally are mounted.

An uplink data bus and a downlink data bus are duplicated between the time slot conversion shelf and the terminal or transmission line interface shelf, and one of the duplexed data buses is a normal data bus that is normally used. The other is an emergency data bus (hereinafter, referred to as a data bus E) used when a normal data bus (hereinafter, referred to as a data bus N) becomes unusable due to a failure or the like.

On the other hand, the time slot conversion shelf and the terminal or transmission line interface shelf have bus buffers corresponding to the data buses in order to increase the reliability of the data to be transmitted. E
And corresponding to being duplicated.

Therefore, when the normal line is switched from the data bus N to the data bus E, the bus buffer also needs to be switched. Normally, this switching requires a certain period of time from when a failure is discovered to when it is completely switched. Digital data (hereinafter, referred to as D data) at the time when the failure is found may be transmitted as it is.

[Conventional technology]

FIG. 8 is a diagram for explaining the structure of a duplicated data bus, and FIG.
FIG. 10 is a diagram for explaining a conventional example of a duplex circuit, and FIG. 10 is a diagram for explaining a time chart in a conventional example of a duplex circuit.

FIG. 8 shows a time slot conversion felt (hereinafter referred to as an SW shelf) 1 constituting a composite synchronous multiplex terminal device and a plurality of terminal interfaces or transmission line interface shelves (hereinafter referred to as IF shelves) # 1 to #N. It shows the structure of the installed double bus.

A bus for transmitting signals from the TSW shelf 1 to the IF shelves # 1 to #N is called a down bus, and the IF shelves # 1 to #N.
A bus for carrying a signal from #N to the TSW shelf 1 is called an up bus, and both a down bus and an up bus have a normal (hereinafter referred to as N) and an emergency (hereinafter referred to as E) bus.

Normally, it is assumed that the TSW shelf 1 has a capacity of 960 TS as the number of time slots (hereinafter, referred to as TS), and each bus in this example exchanges signals at 8 Mbits.

In order to shape the waveform of the signal, the downstream bus N and the upstream bus N are temporarily exchanged with a signal via a bus buffer (hereinafter, referred to as a BUF).
# BUF-N2 for down bus N and up bus N for each N
(1) to 2 (n) and BUF-N3 (1) to 3 (n) provided corresponding to the downstream bus E and the upstream bus E are provided.

FIG. 9 shows the configuration contents of IF shelves # 1 to #N as a representative of IF shelves #i, and BUF-N2 (i) and BUF-E3.
It has the same configuration as (i), and its configuration is
−2N (i).

This configuration is based on an input-side BUF (hereinafter referred to as IN-BUF) 21.
a, output-side BUF (hereinafter referred to as OUT-BUF) 21b, check bit insertion circuit 22, data processing circuit 23, filling time slot check circuit (hereinafter referred to as FTS check circuit) 24, and clock loss detection The circuit 25 includes a circuit 25, a check bit detection circuit 26, and an N / E switching control circuit 27.

In this example, a downstream bus N is taken as an example, and data carried through the bus includes D data and a clock.

The IN-BUF 21a and the OUT-BUF 21b interface with a bus and a terminal device or a transmission line.

The check bit insertion circuit 22 is a circuit that inserts several bits for checking into the first and last check bit areas of one frame of D data output from the IN-BUF 21a. The FTS check circuit 24 checks for an error in the D data. The clock disconnection detection circuit 25 and the check bit detection circuit 26
The N / E switching control circuit 27 includes, for example, an FTS check circuit 24 in the BUF-N2 (i), a clock loss detection circuit 25, and a check bit detection circuit 26. If an error is detected in BUF-E3 (i)
And the output of OUT-BUF21b in BUF-N2 (i) is stopped.

FIG. 10 shows the state and timing of the D data output from the OUT-BUF 21b when an error in the D data is detected by the bits in the check area inserted at the beginning and end of one frame of the D data. I have.

The output of D data from IF shelf #i is BUF-N
2 (i) Selected from OUT-BUF21b, BUF-N
When the 2 (i) side becomes abnormal, it is switched to the BUF-E3 (i) side and is selectively output from the OUT-BUF31b in the BUF-E3 (i).

The failure modes in which these abnormalities occur include transmission abnormalities on the other side that has transmitted the received D data, abnormalities and disconnections in the both-end connector cable (LTG) connected to the shelf, etc.
It is conceivable that a circuit in the UF-N2 (i) fails.

FIG. 10 shows a time chart when these failure modes are detected by the FTS check circuit 24, the clock cutoff detection circuit 25, and the check bit detection circuit 26.

In FIG. 10, in the downlink bus N, the D data (D data 1) of the frame #n is normal, and the frames # n + 1 and #
The case where the D data of n + 2 (D data 2 and D data 3) is abnormal is shown, while the downlink bus E is the case where the D data of frame #n to frame # n + 2 is normal.

According to the check result of the downlink bus N, the frame # n + 1
When the D data abnormality of frame # n + is detected,
The 1 D data is output as it is from the OUT-BUF 21b.

On the other hand, when the D data abnormality of the frame # n + 2 is detected, the frame is switched to the downstream bus E due to the D data abnormality of the frame # n + 1.
D data of +2 (output of OUC-BUF31b) is selected and output.

At the time of output of the OUC-BUF21b (or OUT-BUF31b), the check bit area is output in an empty state.

[Problems to be solved by the invention]

As described above, for example, if the D data abnormality of the frame #i is detected based on the check result of the downlink bus N, it takes a certain time to switch to the downlink bus E side. The abnormal D data at the point of time is output as it is.

Therefore, in the related art, abnormal D data or instantaneous interruption is output as it is at the time of N / E switching.

SUMMARY OF THE INVENTION An object of the present invention is to provide a non-instantaneous interruption switching method of a duplex circuit that always outputs normal D data continuously even at the time of N / E switching of a bus.

[Means for solving the problem]

FIG. 1 is a diagram for explaining the principle of instantaneous interruption switching of a duplex circuit according to the present invention.

The principle diagram of the instantaneous interruption switching of the duplex circuit shown in FIG. 1 is as follows: the input bus buffer 21a, the data processing unit 23, the interruption / abnormality detecting unit 24a, the abnormality detecting unit 26a, and the N / E switching control circuit 27. When,
It comprises a holding unit 28a, a data writing unit 29a, and a data reading unit 29b.
The switching control circuit 27 performs the same operation as that described with reference to FIG. 9, and the disconnection / abnormality detection unit 24a includes the FTS check circuit 24 and the clock disconnection detection circuit 25 described with reference to FIG. The abnormality detecting section 26a has the same contents and the same operation as the check bit detecting circuit 26 also described with reference to FIG. 9, and the holding means 28a converts digital data and a clock input through the input bus buffer circuit 21a. Data processing unit 23
The data writing means 29a creates the timing for writing digital data into the holding means 28a based on the clock, and reads the data. The means 29b creates a timing for continuously outputting the clock even when the disconnection of the clock is detected by the disconnection / abnormality detection unit 24a and reading the digital data held in the holding means 28a. And an abnormality detection unit 26a for detecting an abnormality in the output of the disconnection / abnormality detection unit 24a and the data processing unit 23 in the normal circuit 2 (i).
When the error is detected by the check bit inserted in the digital data in the step (2) and the switching to the margin circuit 3 (i) is performed under the control of the N / E switching control circuit 27, the data reading means is also used.
At 29b, the digital data held in the holding means 28a is read out and sent to the terminal or the transmission line via the output bus buffer 21b.

The provision of such means provides a means for solving this problem.

(Operation)

The received digital data is written into the holding means 28a based on the data writing means 29a.

The holding unit 28a has a capacity for one frame of digital data. For example, an abnormality or disconnection of the received digital data is detected by the disconnection / abnormality detection unit 24a or the abnormality detection circuit 26a, and performs N / E switching of the bus. As for the digital data output at the time, the digital data one frame before written in the holding means 28a is read out by the data reading means 29b.

The digital data one frame before is read by the data reading means 29.
Since the N / E switching of the bus is completed while reading based on b, normal digital data output is continued, so that the output digital data is prevented from being momentarily interrupted or abnormal digital data being output It becomes possible.

〔Example〕

Hereinafter, the gist of the present invention will be described in detail with reference to an embodiment shown in FIGS.

FIG. 2 is a diagram for explaining an embodiment of the instantaneous interruption switching of the duplex circuit of the present invention, FIG. 3 is a diagram for explaining a time chart of instantaneous interruption switching of the duplex circuit in the present invention, and FIG. FIG. 5 is a diagram illustrating a switching case of a duplex circuit according to the present invention; FIG. 5 is a diagram illustrating a filling time slot check state of the duplex circuit according to the present invention; FIG. 7 and FIG. 7 are diagrams for explaining the processing status of the elastic memory of the duplex circuit in the present invention.

The embodiment of the present invention shown in FIG.
This shows the configuration of BUF-N2 (i) in IF shelf #i.
The input / output bus buffers 21a and 21b, the N / E switching control circuit 27, and the data processing circuit 23 described in FIG. 1 as an embodiment of the present invention perform operations similar to those described in FIG. . The input / output bus buffers 21a and 21b are IN-BUF
21a, OUT-BUF21b.

Next, the disconnection / abnormality detection unit 24a shown in FIG. 1 includes an FTS check circuit 24 and a clock disconnection detection circuit 25 that perform the same operation as that described in FIG. It is composed of a circuit 26.

The elastic memory 28 is used as the holding means 28a, and the pulse generator a (hereinafter referred to as P) is used as the data writing means 29a.
An example in which _a pulse generator b (hereinafter referred to as PG _b ) 29 (2) and a tank circuit (hereinafter referred to as TANK) 29 (3) are provided as data reading means 29b. It is.

FIG. 2 is provided with a check bit insertion circuit 22 having the same contents and the same operations as those described in FIG. 9 in addition to the above.

The elastic memory 28 according to the present invention is capable of simultaneously writing and reading information and has a capacity of one frame of D data.

PG _a 29 (1) and PG _b 29 (2) generate the timing for writing and reading the D data in the elastic memory 28, and the TANK 29 (3) generates the timing for the elastic memory 28. Read D data from 28 by N / E of BUF-N2 (i) and BUF-E3 (i)
In order to continue even at the time of switching, the timing generated by PG _b 29 (2) is held for a predetermined time.

FIG. 3 is a time chart at the time of instantaneous interruption switching in the embodiment of the present invention shown in FIG.
The data frame is the same D data 2 as that described in FIG. 10, and the frame configuration is the same as frames #n to #n.
Let n + 2.

Next, the status of D data at the time of reading from the elastic memory 28 is shown. The lower stage shows the check status of BUF-N2 (i) and BUF-E3 (i), and the lower stage shows OUT-status.
The status of selection and output of D data output from the BUFs 21b and 31b is shown.

Fig. 4 shows OUT-BUF21b in BUF-N2 (i) when an error occurs.
FIG. 2 shows the selection status of OUT-BUF31b in BUF-E3 (i). Signals are the same as those shown in FIG.
Indicates an abnormality detection signal, a signal indicates a switching control signal from the BUF-E3 (i), and a signal indicates an ON / OFF control signal for the OUT-BUF 21b.

Case 1 in FIG. 4 shows a situation in which BUF-N2 (i) is switched to a normal BUF-E3 (i) when BUF-N2 (i) becomes abnormal in the middle. In the case where it is abnormal and BUF-E3 (i) is also abnormal, it shows a situation where BUF-N2 (i) is selected.

Next, FIG. 5 shows the status of the FTS check, in which an FTS pattern of 0/1 alternation is inserted in the check bit located at the head of each frame, and the FTS is detected by checking this. In addition to the 0/1 alternation, a pattern of many bits, a parity bit, or the like can be used as the pattern.

FIG. 6 shows the output of TANK 29 (3) when a clock loss is detected and the reading of the elastic memory 28 by this output. TANK 29 (3) shows the time even if the clock loss is detected by the clock loss detection circuit 25. between t _k indicates that for outputting a clock for reading the elastic memory 28.

Reference numeral t _c denotes the clock loss time constant, reference numeral t _m represents the capacitance of Elastic Tech memory 28 of the time conversion.

Time In an embodiment of the present invention t _k, clock loss time constant t
_{Since c} and the time conversion capacity t _m of the elastic memory 28 have a relationship of t _c <t _m <t _k , the BUF-N2 (i) and the BUF
Even when the N / E is switched at -E3 (i), the D side is selected and output without an instantaneous interruption on the output side.

Next, FIG. 7 shows the situation of write / read timing in the elastic memory 28 having the time conversion capacity t _m .

In FIG. 7, DI is a terminal for inputting digital information to the elastic memory 28, WR and RR are reset terminals for writing and reading the elastic memory 28, WC and RC are write / read. The clock terminal and code DO are the output terminals for the read digital information,
“N” at the beginning of frame n, n + 1, and “1 ′”,
"M" and "m '" at the end indicate bits in the check bit area.

In FIG. 7, the reset timing at the time of writing is 2
Each frame (frame n, frame n + 1)
This timing pulse is generated by PG _a 29 (1) and PG _b 29 (2).

Next, the operation of the embodiment of the present invention will be described with reference to FIGS.

As shown in FIG. 3, among the D data and the clock from the downstream bus N, the frame #n of the D data is normal, the frame # n + 1 and the frame # n + 2 detect an abnormality, and the frames #n to # of the downstream bus E are detected. n + 2 is normal.

These D data are written to the elastic memory 28 (in the case of E, the elastic memory 38) at the timing of the clock transmitted at the same time as the D data, and at the same time, the D data of one frame before is stored at the timing of the clock. And is output from OUT-BUF21b (in the case of E, OUT-BUF31b).

The D data and clock written in the elastic memory 28 are checked for abnormality by an FTS check circuit 24, a clock cutoff detection circuit 25, and a check bit detection circuit 26.

A check bit insertion circuit is provided in the first and last check bit areas of each of the frames #n to # n + 2.
At 22, a check bit for checking whether or not the D data is abnormal is inserted.

The check bit is a parity bit or the like, and a check bit such as an FTS pattern is already inserted in the received D data.

When this check bit area is monitored to check for an abnormality in the D data, a signal is sent to the N / E switching control circuit 25 as abnormal when a plurality of abnormalities occur, and the BUF-
This will promote N / E switching between N2 (i) and BUF-E3 (i).

Also select from OUT-BUF21b (OUT-BUF31b in case of E)
The output D data is frame #n as shown in FIG.
Is checked, frame # n-1 (D data 0 (N)) is obtained, and when frame # n + 1 is checked, frame #n (D data 1 (N)) is output.

Therefore, when an abnormality is confirmed in frame # n + 1 of BUF-N2 (i), N / E of BUF-N2 (i) and BUF-E3 (i)
When the switching is started and the frame # n + 2 is switched due to an abnormality, the output from the OUT-BUF 21b is turned off and is output from the OUT-BUF 31b in the D data BUF-E3 (i).

Thus, the elastic memory 28 and TANK 29
By newly providing (3), normal D data can be selected and output without an instantaneous interruption.

〔The invention's effect〕

According to the present invention as described above, it is possible to provide an instantaneous interruption switching method for a duplex circuit that can significantly reduce the occurrence of errors at the time of switching failures in the duplex circuit.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining the principle of instantaneous interruption switching of a duplex circuit of the present invention, FIG. 2 is a diagram for explaining an embodiment of instantaneous interruption switching of a duplex circuit of the present invention, and FIG. FIG. 4 is a diagram for explaining a time chart of instantaneous interruption switching of a duplex circuit, FIG. 4 is a diagram for explaining a switching case of the duplex circuit in the present invention, and FIG. 5 is a diagram illustrating a filling time slot check state of the duplex circuit in the present invention. FIG. 6 is a diagram for explaining the processing status of the tank of the duplexing circuit according to the present invention; FIG. 7 is a diagram for explaining the processing status of the elastic memory of the duplexing circuit according to the present invention; FIG. 9 is a diagram for explaining a conventional example of a duplex circuit, and FIG. 10 is a diagram for explaining a switching timing chart in a conventional example of a duplex circuit. In the figure, 1 is a TSW shelf, 2 (1) to 2 (i) to 2 (n) are BUF-N, 3 (1) to 3 (i) to 3 (n) are BUF-E, and 21a and 31b are IN-BUF, 21b, 31b and OUT-BUF, 22 is check bit insertion circuit, 23 is data processing circuit, 24 is FTS check circuit, 24a is disconnection / abnormality detection unit, 25 is clock disconnection detection circuit, 26 is check bit detection circuit, 26a is the abnormality detection unit, the N / E switching control circuit 27, 28 is elastic memory, 28a holding means, 29 (1), 29 ( 2) PG a / PG b, 29 (3) is TANK and 29a indicate data writing means and 29b indicates data reading means, respectively.

Claims (1)

(57) [Claims] 1. A composite synchronous multiplexing apparatus for synchronizing and multiplexing image data, audio data and user data and transmitting the multiplexed image data, audio data and user data, and a shelf equipped with a time slot conversion unit and a shelf equipped with a terminal or transmission line interface unit (# i), and the transmission line interface shelf (#) corresponding to a duplicated data bus carrying digital data and a clock.
an input bus buffer circuit (21a) for temporarily holding the digital data and clock input / output to / from i) and a normal circuit (2 (i)) for selecting and outputting the digital data from an output bus buffer circuit (21b) ) And a dual circuit consisting of an emergency circuit (3 (i)) selected when the normal circuit (2 (i)) has a fault. The digital data and clock input via the input bus buffer circuit (21a). Means (28a) for holding the data after performing an alarm detection and phase adjustment by a synchronization check in a data processing unit (23), and timing for writing digital data to the holding means (28a) is created based on the clock. Data writing means (29a) for performing the operation, and determining the clock even when the clock disconnection is detected by the disconnection / abnormality detection unit (24a). Data reading means (29b) for continuously outputting the digital data and reading the digital data held in the holding means (28a) as a read timing and providing the data read means (29b) in the normal circuit (2 (i)). An error is detected by the check bit inserted in the digital data at the abnormality detecting section (26a) for detecting an abnormality of the output of the detecting section (24a) or the data processing section (23), and the N / E switching control circuit (27 ), The data reading means (29) is also switched to the margin circuit (3 (i)).
The digital data held in the holding means (28a) is read out in b), and the output bus buffer section (21b)
A non-instantaneous interruption switching method for a duplex circuit, which is transmitted to a terminal or a transmission line via a communication line.