JP2655738B2 - Switching system between redundant system and single system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] Regarding the redundant system-single system switching system for forcibly switching the ACT state to the SBY state, correct system switching even when a failure such as a clock stack of the redundant system occurs A first extraction circuit connected to the data transfer path and extracting a frame clock, a master clock, and a frame;
A second extraction circuit for extracting system switching identification information inserted into the frame in response to the frame clock, the master clock, and the frame, and performing system switching to a system switching unit between a duplex system and a single system. In a duplexer for transferring an identification signal, an out-of-synchronization detection circuit that generates an out-of-synchronization alarm from the frame clock and the master clock, a stack monitoring circuit that detects a stack of the master clock, the second extraction circuit, A frame synchronization loss detection circuit, and a mask processing circuit connected to an output of the stack monitoring circuit, wherein the mask processing circuit outputs the frame synchronization loss detection circuit and the stack monitoring circuit when the detection signal is not output.
The output signal of the second extraction circuit is output as it is, and when the out-of-frame detection circuit and the stack monitoring circuit output the detection signal, the standby system identification signal is output.

[Industrial applications]

The present invention provides a method for transferring a system switching identification signal to a redundant system-single system switching unit when a failure occurs in a redundant system.
The present invention relates to a dual system-single system switching system for forcibly switching an ACT state to an SBY state.

In a digital exchange and the like, the main part has a double structure in order to enhance the reliability of the system. However, the terminal devices connected to the duplex configuration have a single configuration in order to reduce costs. Therefore, in the operation of the system, in order to perform signal transfer from the duplex system to the simplex system, it is necessary to notify the duplex system-single system switching circuit of the simplex device of which system the duplex system is operating. Becomes indispensable.

[Conventional technology]

FIG. 4 shows a system configuration of a conventional digital exchange. In this figure, a network interface 22 of system 0, a network 24 of system 0, a network interface 26 of system 1 and a network 28 of system 1 show the essential parts of the digital exchange in a duplex configuration. The network 24 of the system 0 indicates the system 0 of the redundant configuration, and the network interface 26 of the system 1 indicates the system 1 of the redundant configuration. 23 is a synchronization device. As shown in FIG. 5, the 0-system network interface 22 and the 1-system network interface 26 include an optical module 40,
It was composed of a synchronization establishment circuit 42, a synchronization establishment counter circuit 44, an ACT signal extraction circuit 46, and an audio data / housekeeping editing circuit 48.

The unifying device 20 is an interface circuit between the duplex system and the unified system in the digital exchange, and includes an ACT selection control circuit 30, a 2-1 selector 32, and a terminal processing circuit 34 as shown in FIG.

The ACT selection control circuit 30 in the single unit 20 receives an ACT selection signal from the 0-system network interface 22 or the 1-system network interface 26, and receives data, clock (CLK), The multi-frame clock (MFCK) is transferred to the terminal device through the 2-1 selector 32 and the terminal processing circuit 34. The generation of the ACT selection signal is performed as follows.

The frame clock (FC
K) and a master start clock (for example, an 8 MHz clock), a count start / stop signal is output from the synchronization establishing circuit 42. The count start / stop signal is input to the synchronization establishment counter circuit 44 to obtain an ACT extraction clock (CLK) from the master clock. Using the ACT extraction clock, the ACT signal extraction circuit 46 outputs the second frame in each frame constituting the multi-frame (see (1) in FIG. 6) output from the optical module 40 onto the data highway 41.
The ACT information (for example, an alternating bit sequence of “1” and “0”) inserted in the first pit insertion area (see (2) and (3) in FIG. 6) of the time slot TS1 and the third time slot TS2 is The ACT identification signal is extracted for each time slot of each frame, and when both time slots are “1”, for example, an ACT identification signal of “H” level is generated. If the system is not in ACT (if both time slots are other than “1”), the ACT signal extraction circuit 46 outputs an “L” level SBY identification signal.

The operation of extracting the ACT identification signal or the SBY identification signal is performed for each system. ACT selection control which is output from the ACT signal extraction circuit 46 of each system and receives a system switching identification signal [ACT identification signal or SBY identification signal (an inverted signal of the ACT identification signal)] via the system switching identification signal lines 43 and 45. If the circuit 30
The system selection signal is sent to one selector 32, and the audio data / housekeeping editing circuit of the system corresponding to the system selection signal is sent.
Each signal output from 48 is selected by the 2-1 selector 32 and transferred to the terminal device via the terminal processing circuit 34.

[Problems to be solved by the invention]

Generation of the system switching identification signal in the transfer control of the signal from the duplex system to the simplex system as described above, as long as the transfer is normally performed, to transfer the signal from the duplex system to the simplex system, No problem.

However, a state (stack state) occurs in which the ACT signal extraction circuit 46 cannot extract and update the ACT information on the data highway 29. This is because, for example, no optical data is received from the ACT 0 network 24 or the 1 system network 28 via the optical data link 29, or the frame clock is extracted due to some failure occurring in the optical data link 29. If the ACT information cannot be extracted, the ACT extraction clock is not output from the synchronization establishing counter circuit 44, so that the ACT signal extraction circuit 46 cannot extract the ACT information.

In such a state, the stack state is transferred to the unified terminal apparatus, so that the state is changed from the unified terminal apparatus via the upstream signal transfer system to the 0-system network interface 22 or the 1-system. The data is transferred to the network interface 26, from which the 0-system network 24,
Alternatively, the data is transferred to the first network 28. The 0-system network 24 or the 1-system network 28 detects an out-of-frame alarm. By this detection, the network 24 of the 0 system or the network 28 of the 1 system
System switching between the system operating as the system and the system operating as the SBY system starts.

However, when a system switchover is performed in the network, the above-mentioned stack status occurs, or if the stack status has occurred, the ACT information cannot be extracted for the relevant system even if the system has been switched to the ACT system. Therefore, the system switching identification signal from the system to the ACT selection control circuit 30 of the unifying device 20 is the SBY identification signal as before, and the system switching identification signal from the system previously operating as the ACT system is The system switching identification signal to the ACT selection control circuit 30 of the optimization device 20 is still an ACT identification signal. A
The system selection signal output from the CT selection control circuit 30 is maintained in the previous state. Therefore, the 2-1 selector 32
The data and clock transferred from the terminal to the unified terminal device via the terminal processing circuit 34 are those of the faulty system, and it is impossible to switch the system properly.

The present invention has been created in view of such problems,
It is an object of the present invention to provide a system switching method capable of correctly performing system switching without being affected by a failure such as a clock stack generated in a redundant system.

[Means for solving the problem]

FIG. 1 is a block diagram showing the principle of the present invention. As shown in this figure, the present invention is connected to a data transfer path and extracts a frame clock, a master clock, and a frame, and a first extraction circuit 1 responsive to the frame clock, the master clock, and the frame. A second extraction circuit 3 for extracting the system switching identification information inserted in the frame
The present invention relates to an improvement in the generation of the system switching identification signal of a duplexer which has a system switching identification signal for each system and transfers the system switching identification signal to a system switching unit between a duplex system and a single system. The present invention includes a frame synchronization loss detection circuit 5 for generating a frame synchronization loss alarm from the frame clock and the master clock, a stack monitoring circuit 7 for detecting a stack of the master clock, the second extraction circuit 3, An out-of-synchronization detection circuit 5 and a mask processing circuit 9 connected to the output of the stack monitoring circuit 7 are provided. The mask processing circuit 9 uses the out-of-synchronization detection circuit 5 and the stack monitoring circuit 7 to detect the detection signal. When not outputting, the output signal of the second extraction circuit 3 is output as it is, and when the out-of-frame detection circuit 5 and the stack monitoring circuit 7 output the detection signal, the standby system identification signal is output. It is composed.

[Operation] In a state where the first extraction circuit 1 of each system of the duplexing apparatus normally extracts the frame clock, the master clock, and the frame, the second extraction circuit 3 extracts the system switching identification information. Frame loss detection circuit 5
Continues to output a signal indicating the frame synchronization state,
The stack monitoring circuit 7 continues to output a signal indicating that the master clock is not stacked. Therefore, as long as the system switching operation does not occur, the active system identification signal is continuously generated from the mask processing circuit 9 belonging to the active system, and the standby system identification signal is continuously generated from the mask processing circuit 9 belonging to the standby system. The dual system-single system switching unit that receives these two system switching identification signals is kept in the system switching state.

When a failure occurs in the frame clock, the master clock, and / or the frame extracted from the first extraction circuit 1 of the duplexer, the second extraction circuit 3, the out-of-frame detection circuit 5, and / or the stack monitoring circuit 7, a signal indicating system switching identification information, an out-of-synchronization alarm, and / or a signal indicating the stack of the master clock is generated. When a system switchover occurs due to such a failure state or the like, the extraction circuit 3 of the system that was operating as the active system before the system switchover according to the cause of the failure outputs the system switchover identification signal to the active system. Even if the identification signal is stuck, the active system identification signal is output from the mask processing circuit 9 as a standby system identification signal. Therefore, the system switching corresponding to the system switching in the redundant system is also caused in the redundant system-single system switching system.

Therefore, a malfunction of the system switching between the duplex system and the single system does not occur due to the failure of the duplex system. Obstacle waves to the system down can be prevented.

〔Example〕

FIG. 2 shows an embodiment of the present invention. The same components as those in FIG. 5 described in the section of “Prior Art” include
The same reference numerals are given and the description is omitted. In FIG. 2, a synchronization establishing circuit 50, a counter stack monitoring circuit 5
2. The AND circuit 54 is a new component requirement. The synchronization establishing circuit 50 outputs an out-of-frame synchronization alarm in addition to the count start / stop signal generation function.

The configuration is shown in FIG. The circuit is a counter 60,
It comprises a TS0 recognition circuit 62, a D flip-flop circuit 64, a D flip-flop circuit 66, and a NAND circuit 68. The counter 60 is initialized by the frame clock and counts up the master clock. The frame clock is set to the D flip-flop circuit 64 by the output of the TS0 recognition circuit 62, and the output of the D flip-flop circuit 64 is set to TS.
In response to the output of the 0 recognition circuit 62, the frame clock is set in the D flip-flop circuit 66. Naand circuit 68
Receives the outputs of the D-flip-flop circuit 64 and the D-flip-flop circuit 66, and outputs an "L" level out-of-frame alarm.

The counter stack monitoring circuit 52 receives the master clock, monitors the stack state, and outputs an “L” level signal when the stack state occurs. For example, it is a circuit including a D-flip-flop circuit 64, a D-flip-flop circuit 66, and a NAND circuit 68 shown in FIG. At that time, the circuit uses a master clock instead of the frame clock shown in FIG. 3, and uses an "H" level signal instead of the output of the TS0 recognition circuit 62.

In FIGS. 1 to 3, the optical module 40 is the first optical module.
The synchronization establishment circuit 50 and the synchronization establishment counter circuit 44 correspond to the first extraction circuit 1 in FIG. 1, and correspond to the second extraction circuit 3 in FIG. The synchronization establishing circuit 50 corresponds to the frame out-of-synchronization detecting circuit 5 in FIG.
Corresponds to the stack monitoring circuit 7 in FIG. The AND circuit 54 corresponds to the mask processing circuit 9 in FIG.

The operation of the network interface forming the ACT identification signal generation circuit as described above will be described below.

Now, in the current system, the frame clock FC
Suppose that a stuck state occurs in K. The occurrence of this state continues to generate an ACT identification signal indicating that the system is in the ACT system from the ACT signal extraction circuit 46, as described in the section of "Prior Art". The counter stack monitoring circuit 52 continues its normal operation. However, the frame out-of-synchronization alarm circuit of the synchronization establishing circuit 50 detects the abnormal state of the frame clock FCK supplied thereto,
The information set in the D flip-flop circuit 64 and the D flip-flop circuit 66 differs due to an error in the TS0 recognition information set in the flip-flop circuit 64 and the D flip-flop circuit 66 or the abnormality of the frame clock FCK. Therefore, an out-of-frame alarm is output from the NAND circuit 68.

Therefore, the AND circuit 54 generates an SBY identification signal. This is the frame clock FCK of the active system.
Even if a stack state occurs, this is equivalent to the correct system switching at the duplex-single-system interface when the duplex switching is correctly performed.

Even when a stack state occurs in the master clock of 8 MHz, in this case, the stack state is detected by the counter stack monitoring circuit 52 and the “L” level signal is transferred to the AND circuit 54. FCK
As in the case of the occurrence of the stack state, the system switching at the duplex system-single system interface can be performed correctly.

Also, when the frames on the data highway 41 are stacked, the system switching identification information input to the ACT signal extraction circuit 46 is not correctly transferred, that is, the information is not the alternating information. , And the SBY identification signal is supplied to the AND circuit 54. Therefore, also in this case, system switching at the duplex system-single system interface can be correctly performed.

Further, even if an optical cable disconnection that simultaneously generates a frame clock stack, a master clock stack, and a frame stack on the data highway 41 of the system in the working system occurs, the duplex system-single system is used as described above. System switching can be performed correctly using the virtualization system interface.

Although the above embodiment has been described with reference to the case where data is transferred in a multiframe in the digital exchange, the frame need not be a multiframe. Although the description has been given of the duplex system-single system interface in the digital exchange, the present invention is equally applicable to other similar duplex system-single system interfaces.

〔The invention's effect〕

As is apparent from the above description, according to the present invention, it is possible to eliminate the influence of a failure occurring in the redundant system on switching between the redundant system and the single system. Therefore, it helps to prevent the system from going down.

[Brief description of the drawings]

1 is a block diagram showing the principle of the present invention, FIG. 2 is a diagram showing an embodiment of the present invention, FIG. 3 is a diagram showing an out-of-frame alarm generating circuit, FIG. 4 is a system configuration diagram of a digital exchange, FIG. 5 is a configuration diagram of a network interface, and FIG. 6 is a diagram showing a position where ACT information of a multi-frame is inserted. 1 to 3, reference numeral 1 denotes a first extraction circuit (optical module 40), and 3 denotes a second extraction circuit (synchronization establishment circuit 50, synchronization establishment counter circuit 4).
4) 5 is a frame loss detection circuit (synchronization establishment circuit 5)
0) and 7 are stack monitoring circuits (counter stack monitoring circuit 52), and 9 is a mask processing circuit (AND circuit 54).

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical indication H04Q 3/545 H04Q 3/545 11/04 11/04 M

Claims (1)

(57) [Claims] A first extracting circuit connected to a data transfer path for extracting a frame clock, a master clock, and a frame; and a first extracting circuit for extracting the frame clock, the master clock, and the frame. Second extraction circuit (3) for extracting inserted system switching identification information
And a frame out-of-synchronization detecting circuit (5) for generating a frame out-of-synchronization alarm from the frame clock and the master clock. A stack monitor circuit (7) for detecting a stack of the master clock; a mask connected to outputs of the second extraction circuit (3), a frame out-of-synchronization detection circuit (5); and a stack monitor circuit (7). A processing circuit (9), wherein the mask processing circuit (9) outputs an output signal of the second extraction circuit 3 when the out-of-frame detection circuit 5 and the stack monitoring circuit 7 do not output the detection signal. Is output as it is, and when the out-of-frame detection circuit 5 and the stack monitoring circuit 7 output the detection signal, the standby system identification signal is output. A system switching method between a duplex system and a single system, which outputs a signal.