JP3388335B2 - Multi-frame phase matching circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-frame phase matching circuit.

[0002]

2. Description of the Related Art In addition to a current transmission line, data provided with multi-frames needs to be switched to a backup transmission line without interruption when there is a failure. However, since the transmission line lengths of both are different, a delay in data frame occurs on the working and protection transmission lines. If there is a delay on this frame, when switching is performed, bit skipping, duplicate bits, etc. occur, and accurate transmission cannot be performed. Therefore,
Attempts have been made to insert a delay circuit and the like so that the transmission line lengths of the working and protection lines are the same so that the transmission lines have the same phase.
If the phases of both transmission signals are the same, it is possible to switch appropriately, and there is no problem at the time of failure, repair, or inspection.

Although a bit error of about 1 bit occurs at the time of switching, it does not become a practical obstacle, depending on the type of lower connection. In any case, it is important to match the same phase. However, such a conventional technique has a drawback that the operation of a circuit for creating a phase for memory reading for multi-frame phase alignment becomes complicated and the circuit scale becomes large.

The first conventional technique is described in Japanese Patent Application Laid-Open No. 4-1560.
This will be described with reference to the block diagram of FIG. 4 showing the configuration disclosed in Japanese Patent Laid-Open No. 22 and the timing chart of FIG. 5 showing its operation. In this configuration, the data (0) and data (1) clocks are reproduced from the received data, and the dual port memories 55 and 56 that can arbitrarily write and read (1),
Address control circuits 57 and 58 that generate write address signals for the dual port memories 55 and 56 from the clocks of the receiving circuits 51 and 52, and address control circuits 59 that generate read address signals of the dual port memories 55 and 56 from the reference clocks. 2 and a frame synchronization circuit 53, 54 for identifying the reception frame number from the received data, and compares the reception frame number identification signals from the respective frame synchronization circuits 53, 54 for comparison. Phase comparison circuit 61 for generating a clock
And a data selection circuit 63 for selecting the output of each of the dual port memories 55 and 56 by a data selection signal.
And an alarm control circuit 6 which outputs a data selection signal using the out-of-synchronization signals from the receiving circuits 51 and 52 as inputs.
2 and the receiving circuits 51 and 52 detect a loss of synchronization, the alarm control circuit 62 outputs a data selection signal for selecting normal data, and the write addresses to the dual port memories 55 and 56. The phase difference between the address control circuits 57, 58 for generating signals and the address control circuits 59, 60 for generating read address signals is set to 3 frames or more of received data.

However, in such a frame phase synchronizing circuit, receiving the frame number identification signal is an essential function in the structure.

Further, referring to the block diagram of FIG. 6 as a second conventional technique, frame synchronization circuits 3 and 4 for establishing a frame phase of received data, and a frame phase established by the synchronization circuits 3 and 4 are used as references. , N frames are one multi-frame, data is written in a multi-frame cycle, and data is written and read in arbitrary memories 32 and 33 and a read address signal for supplying a read phase of the memories 32 and 33. When the comparison circuit 25 has two circuits configured by the generation circuit and compares the data outputs of the memories 32 and 33 to determine whether they match, and the comparison circuit 25 detects a mismatch,
It is composed of a read control circuit 29 for individually controlling the read address signal generating circuits of the above two circuits, and the following operation is performed.

Frame synchronization of the plurality of received signals S1 and S2 is established. The received signals S are stored in the memories 32 and 33, respectively.
1 and S2 are written in frame units and in a multi-frame cycle . The outputs of the memories 32 and 33 are compared, and if they match, it is determined that the read phase at that time is correct, and the state is maintained as it is. If the comparison results of the outputs of the memories 32 and 33 do not match, the read phase of one of the memories is fixed, and the read phase of the other is shifted in units of one frame. If the read phases of the memories are shifted by one frame and the outputs of the memories 32 and 33 match, the phase can be determined to be the phase in which the phases of the received signals can be matched by the memories. Hold the phase. On the contrary, if the outputs of the memories 32 and 33 do not match even if the memory read phase is shifted by one frame, the received signals are not phase-matched, and the above steps are repeated. If the coincidence point of the memory output cannot be detected even if the operation of-is repeated for the writable capacity of the memory, the memory read of the one in which the initial state memory phase is shifted in frame units is fixed, The reading phase of the memory in which the reading phase of the initial state memory is fixed is switched so as to be shifted in units of frames, and the above-mentioned is repeated.

[0008]

The above-mentioned first conventional technique requires the addition of a frame number identification signal for phase determination, and cannot be realized if the frame signal format is already fixed and cannot be changed. Further, in the above-mentioned second conventional technique, it is not necessary to add the frame number identification signal, but the operation / circuit for determining the memory read phase becomes complicated / large-scale.

Therefore, an object of the present invention is to provide a multi-frame phase matching circuit which does not require a special signal for identifying a frame number and has a simple structure for phase matching.

[0010]

In order to solve the above-mentioned problems, a multi-frame phasing circuit according to the present invention is a frame for establishing frame synchronization of first and second input signals having different leading phases of multi-frames. The synchronization means, the first storage means for reading in the same frame phase, and the read first and second input signals for an arbitrary n (n is larger than 2).
N is a positive integer)
The second storage means for storing at the frame period and the both signals of the result of sampling at the n- frame period from the read first input signal and the result of sampling at the frame period from the second input signal are compared. A first comparator, and a second comparator for comparing both the result of sampling from the read first input signal at a frame period and the result of sampling from the second input signal at a period of n frames. A first control for delaying and outputting the second signal based on the coincidence result of the second comparator when the first signal is later than the second signal Means and second control means for delaying and outputting the first signal based on the first comparator when the first signal leads the second signal. Consists of

Here, the first and second storage means are dual port memories capable of arbitrarily writing and reading, and the first and second control means are respective memories and the memory. The read timing is the first,
It has a read control circuit based on the comparison of the second comparator.

[0012]

DETAILED DESCRIPTION OF THE INVENTION A first embodiment of a multi-frame phasing circuit of the present invention is shown in FIG. Figure 3
FIG. 4 is a timing chart showing the operation of the first embodiment. 1 and 3, the first embodiment of the multi-frame phase adjusting circuit of the present invention is the same as the frame synchronizing circuits 3 and 4 for the first and second input signals S1 and S2 having different multi-frame head phases. , Frame memories 9 and 10 for reading both of them in the same frame phase, and the first or second signal S1 or n of S1 (n is a positive integer greater than 2 )
Frame counter 15 and output n of this counter 15
Of the first input signal S1 for n frame periods and the results of sampling for the second input signal S2 at frame periods for comparing both signals. A comparison circuit 25,
A second comparison circuit 26 that compares both signals of the second input signal S1 and the result of sampling at the frame period, and the first input signal S1 is delayed from the second input signal S2. On the basis of the matching result of the second comparison circuit 26, the second input signal S2 is delayed and output, and the first input signal S1 leads the second input signal. In this case, the first comparison circuit 25
Control means for delaying and outputting the first input signal S1 based on
9 and.

The configuration of the second embodiment of the multi-frame phase matching circuit of the present invention is shown in the block diagram of FIG. 2, the n-frame cycle sampling circuits 17 and 19 shown in FIG.
39, the frame period sampling circuits 18, 2 of FIG.
0 is a frame cycle CRC (Cyclic Redund
The device has been replaced with the operation circuits 37 and 40, and the front and rear connection relationships and the functions thereof are common. Since the other block portions are common to those in FIG. 1, they are illustrated by using common reference numerals, and their functions and effects will not be described again.

Here, the above-mentioned frame cycle CRC calculation circuits 37 and 40 are also connected to BIP-L (Bit Interleaved).
Parity-L) check circuit can be replaced. In both cases, the frame period sampling circuits 18 and 20,
It exhibits a similar function.

Originally the same signal, the signals S1 and S2 of FIG. 3 input via different paths for improving the reliability of the system are respectively synchronized by the frame synchronization circuits 3 and 4. From these synchronizing circuits 3 and 4, a signal S5 equivalent to the signal S1, a frame signal S6 indicating the frame phase of this signal S5, and a signal S2 equivalent to the signal S2.
7 and a frame signal S indicating the frame phase of this signal S7
8 and 8 are output respectively. The signals S5 and S7 are frame signals S6 and S6 respectively indicating the established frame phase.
It is written in the frame memories 9 and 10 in the phase of S8,
As shown by the signals S11 and S13 in FIG. 3 by being read in the same frame phase, the signal S11 and the frame signal S12 showing the frame phase of this signal S11 and the signal equivalent to the signal S2 have the same frame phase. S1
3 and a frame signal S14 indicating the frame phase of this signal S13 are output. However, the frame signal S1
2 and S14 are the same data. A frame signal S12 indicating the frame phase of the signal S11 is input to an n-frame counter 15 that counts n frames at the frame phase, and outputs a multi-frame signal S16 having an n-frame cycle.

The multi-frame signal S16 is the signal S11.
Is supplied to a first n-frame period sampling circuit 17 for sampling the signal S11 once every n frames,
It serves as a timing signal for sampling the frame period and stores the signals S11 and S13 in memory 32 and 33.
, And also serves as a reference signal for the read control circuit 29 to determine the memory read phase by the outputs of the comparison circuits 25 and 26.

The input signals S11 and S13 having the same frame phase are separately written in the memories 32 and 33 with reference to the multi-frame signal S16 indicating the multi-frame phase of n frame periods. The signals S11 and S13 having the same frame phase are output to the n frame period sampling circuits 17 and 19 and the frame period sampling circuit.
18 and 20, the data of the same section in the frame is sampled in an arbitrary quantity, and the signals S21 and S23 of the n frame cycle sampling result and the signals S22 and S24 of the frame cycle sampling result are obtained.

As described above, the signal S21 as a result of sampling the signal S11 at the n-frame cycle and the signal 24 as a result of sampling the signal S13 at the frame cycle are sampled by the comparison circuit 25, and the signal S11 is sampled by the frame cycle. A comparison circuit 26 compares the resulting signal S22 and the resulting signal S23 obtained by sampling the signal S13 at n frame periods.

Since the signals S1 and S2 are originally the same signal, if the signal S2 is delayed with respect to the signal S1, the frames of the signal S21 and the signal S13 of the n frame period sampling result of the signal S11 are obtained. Although the signal S24 of the periodic sampling result may match, the signal S22 of the frame periodic sampling result of the signal S11 is obtained.
And the signal S of the frame period sampling result of the signal S13
23 cannot match, so the signal S in FIG.
27 and S28, the first comparison circuit 25 determines that there is a match, and the second comparison circuit 26 does not detect a match.

On the contrary, when the signal S2 is ahead of the signal S1, the signal S22 of the frame period sampling result of the signal S11 and the signal S23 of the n frame period sampling result of the signal S13 coincide with each other, and The second comparison circuit 26 determines that they match, and the first comparison circuit 25 does not match.

At this time, the read control circuit 29 reads the signal of one of the memories 32 and 33, which has been determined to have arrived with a delay in the read phase, at the timing of the coincidence detection, and determines that the signal has arrived first. Signal is
By controlling the reading to start at the phase delayed by the phase difference, the data in which the multi-frame phases match are output as the output signals S34 and S35, respectively.

As described above, according to the embodiment of the present invention,
Originally, by transmitting the same signal via different transmission paths to create a redundant configuration, when signals are received in a state where the phases are different, in order to execute various processing such as switching without interruption. , As shown by signals S34 and S5 in FIG. The operation of this embodiment is performed as follows.

(1) The respective frame synchronizations are established by the synchronizing circuit for the respective input signals having different frame start phases and multi-frame start phases via different transmission paths. (2) The input signal is written at the frame phase established by the synchronization circuit and written / read to / from the frame memory to be read at the same frame phase, thereby matching the frame phases of the signals. Here, dual port memories are used as the memories 9 and 10. (3) The output of the frame memory is also written in each memory at an n-frame cycle. (4) The input signal is sampled in m (m is an integer greater than 1) bits in each n frame periods. A sample of the signal A is referred to as A1, and a sample of the signal B is referred to as B1. (5) m bits of the input signal are sampled at each frame period. The signal A sampled is A2, and the signal B sampled is B2. (6) The results of sampling above are A1, B2, and B1.
And A2 are compared to detect the coincidence. (7) For example, as a result of the match detection in (6) above, A1 and B
If the two match, it can be determined that the signal B arrives later than the signal A. Therefore, the signal B can be normally read based on the read phase of the memory 32 based on the multiframe head phase of the signal B. By setting to, the multiframe head phases of the signal A and the signal B are matched.

By adding or substituting the following circuits to the above basic functional configuration, it is possible to further improve the accuracy and reduce the circuit scale.

The larger the number of samplings m, the higher the accuracy of position detection, but the larger the number m, the larger the circuit scale. CRC (Cycl
ic Redundancy Check) arithmetic circuit or BIP-L (B
It Interleaved Parity-L) can improve accuracy and simplify the circuit.

When there is no phase difference between the signals, coincidence detection is performed on both A1 and B2 and A2 and B1 obtained above. In this case, the read phase is set with reference to the multi-frame head phase from either the signal A or the signal B (which is set in advance).

[0027]

As described above, according to the multi-frame phasing circuit of the present invention, the memory read phase is not determined by the phase determination based on the frame number identification signal, but by the data comparison result, the frame synchronization is achieved. Even when the frame identification number cannot be added / changed to the signal for use, multi-frame phase matching is possible, and by providing the data comparison circuit in front of the memory, the phase matching operation can be easily realized and the circuit scale can be reduced. , And a data comparison circuit, for example, CR as in the first embodiment.
By replacing the circuit with the C check circuit or the BIP-L arithmetic circuit, it is possible to reduce the size of the circuit while maintaining the accuracy of comparison.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of a multi-frame phase matching circuit of the present invention.

FIG. 2 is a second multi-frame phasing circuit of the present invention.
3 is a block diagram showing the configuration of the embodiment of FIG.

FIG. 3 is a timing chart showing an operation of each unit of the first embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a first conventional technique.

FIG. 5 is a timing chart showing an operation of each unit of the first conventional technique.

FIG. 6 is a block diagram showing a configuration of a second conventional technique.

[Explanation of symbols]

3, 4 frame synchronization circuit 9, 10 frame memory 15 n frame counter 17, 19 n frame cycle sampling circuit 18, 20 frame cycle sampling circuit 25, 26 comparison circuit 29 read control circuit 32, 33, 55, 56 memory 36, 39 n frame cycle holding circuit 37, 40 frame cycle CRC calculation circuit 51, 52 receiving circuit 53, 54 frame synchronizing circuit 57, 58, 59, 60 address control circuit 61 phase comparison circuit 62 alarm control circuit 63 data selection circuit

─────────────────────────────────────────────────── --- Continuation of front page (56) References JP-A-4-156022 (JP, A) JP-A-9-266469 (JP, A) JP-A-2-226928 (JP, A) JP-A-6- 188864 (JP, A) JP 7-79208 (JP, A) JP 5-63686 (JP, A) JP 4-175023 (JP, A) JP 4-37336 (JP, A) JP-A-2-309729 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04J 3/00-3/26 H04L 5/22-5/26 H04L 1/00 H04L 7 / 00 JISST file (JOIS)

Claims (3)

(57) [Claims] 1. A frame synchronization means for establishing frame synchronization between first and second input signals having different head phases of a multiframe, a first storage means for reading at the same frame phase, and a read first memory means. the optional first and second input signals
n (n is a positive integer greater than 2) frames
A second storage unit that stores a frame at an n-frame cycle, a result obtained by sampling the read first input signal at an n- frame cycle, and a result obtained by sampling the second input signal at a frame cycle. A first comparator for comparing signals, and a second comparator for comparing both signals of a result of sampling from the read first input signal at a frame period and a result of sampling from a second input signal at an n frame period And the first signal lags behind the second signal, the second signal is delayed and output based on the coincidence result of the second comparator. A first control means and a second control for delaying and outputting the first signal based on the first comparator when the first signal leads the second signal And means Multi-frame phase matching circuit to be. 2. The multi-frame phase adjustment circuit according to claim 1, wherein the first and second storage means are dual port memories capable of arbitrarily writing and reading. 3. The first and second control means have respective memories and a read control circuit for performing a read timing of the memories based on the comparison of the first and second comparators. 1. The multi-frame phase matching circuit described in 1.