JP2819955B2 - In-device error monitoring circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an in-device error monitoring circuit, and more particularly to an in-device error monitoring circuit for monitoring data errors in a device using digital transmission.

[0002]

2. Description of the Related Art As shown in FIG. 3, a conventional error monitoring circuit in a device calculates a parity of write data 1 and inserts a parity bit into a vacant bit. The write data is controlled by a write control pulse 2, input by a write clock 3 and controlled by a read control pulse 6, and an elastic store 4 for outputting read data 5 by a read clock 7 and read data 5, A parity error detection circuit 19 that performs a parity operation, determines whether or not there is a data error by comparing with the parity bit added by the parity operation addition circuit 18, and outputs the data error information 17. I have.

[0003]

The conventional error monitoring circuit in the apparatus requires a surplus bit for adding a parity operation result in order to detect a data error, and its application range is limited.

Further, there is a problem that an error cannot be detected with respect to an error of a plurality of bits because of an error detection system using parity.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and eliminate the need for extra bits for data error detection.
It is another object of the present invention to provide an in-device error monitoring circuit capable of reliably performing error detection even for errors of a plurality of bits.

[0006]

An error monitoring circuit in a device according to the present invention controls write data by a write control pulse and inputs it by a write clock, and controls read data by a read control pulse and outputs it by a read clock. Data write / read means for securing the frequency synchronization between the write clock and the read clock by PLO; delay amount detection means for detecting a delay time from writing to reading of data in the data write / read means; PLO monitoring means for monitoring the write control pulse and the read control pulse and outputting stable / unstable operation information of the PLO; variable delay means for inputting the write data and providing a delay of the delay time; The output data of the delay means and the read data are compared one bit at a time. A data comparing means for confirming a match and a mismatch and outputting data error information when there is a mismatch, and receiving the stable / unstable operation information of the PLO and receiving the data error information from the data comparing means only when the stable operation information is input. And output control means for outputting.

[0007]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a basic configuration of an in-device error monitoring circuit according to one embodiment of the present invention.

In the embodiment shown in FIG. 1, an elastic store 4 as data writing / reading means, a data write control pulse in the elastic store 4 is read, and data writing to reading is performed by measuring a distance of the control pulse on a time axis. And a PLO monitoring circuit 9 as PLO monitoring means for monitoring the synchronous and asynchronous states of the PLO.
A variable delay circuit 9 as a variable delay means for giving a delay amount from data writing to reading to input write data, and a bit-by-bit conversion between read data from the elastic store 4 and delay data output from the variable delay circuit 10. Data comparison circuit 14 as data comparison means for outputting data error information when no match is found, and output of data error information output from data comparison circuit 14 when PLO is in an unstable operation state And an output control circuit 16 as output control means for suppressing the above.

FIG. 2 is a block diagram showing a specific configuration example of the in-device error monitoring circuit according to one embodiment of the present invention.

The configuration shown in FIG. 2 includes the same elastic store 4 as in FIG. 1, a PLO 20, a write-side frame counter 22, and a read-side frame counter 23 which specifically form the delay amount detection circuit 8 in FIG. 1, a slip amount calculating circuit 21 corresponding to the delay amount detecting circuit 8, a slip detecting circuit 24, flip-flops 25 and 26, a coincidence detecting circuit 27, and an OR which specifically form the PLO monitoring circuit 9 in FIG.
It has a configuration including a circuit 28 and the same variable delay circuit 10, data comparison circuit 14, and output control circuit 16 as in FIG.

Next, the operation of this embodiment will be described with reference to FIG.

The write data 1 is written into the elastic store 4 by the write clock 3 under the control of the write control pulse 2.

The write data 1 is read by a read clock 7 under the control of a read control pulse 5.

The frequency synchronization between the write clock 3 and the read clock 7 is ensured by the PLO 20. Therefore, when the PLO 20 is in a stable operation state, the delay from the data input to the data output of the elastic store 4 is equal to the write clock 3 , And a fixed value of the value calculated by the delay amount calculating circuit 21 based on the respective outputs of the write-side frame counter 22 operated by the read clock 7 and the read-side frame counter 23 operated by the read clock 7.

Therefore, this delay amount is set in the variable delay circuit 10, and the input data of the elastic store 4 is converted into the data output through the variable delay circuit 10 and the output data of the elastic store 4 bit by bit. An error can be detected by comparing the data with the data comparison circuit 14 in bibits.

On the other hand, when the PLO 20 is in an unstable operation state, that is, during the synchronization pull-in operation or the change of the steady phase error, the delay amount from the data input to the data output of the elastic store 4 changes every hour. Therefore, the data comparison circuit 14 cannot correctly detect an error.
In this case, the output control circuit 16 controls the data error information 17 so as not to be output.

In the state where the PLO 20 is in the pull-in state, the collision between the write control pulse 2 and the read-out control pulse 6 is monitored by the slip detection circuit 24 paying attention to slip detection. I do.

In the steady phase error changing state, the output of each of the write-side frame counter 22 and the read-side frame counter 23 is changed at two consecutive times when the value calculated by the delay amount calculation circuit 21 is sampled. Whether or not they are different is detected by the coincidence detecting circuit 27 with respect to the result passed through the flip-flops 25 and 26, and if they are different, it is determined that the steady phase error is changing.

The detection output of the slip detection circuit 24 and the detection output of the coincidence detection circuit 27 are both supplied to an OR circuit 28. If any one of the detection outputs is present, the detection output is provided as control information of the output control circuit 16, and Error information 1
76 is suppressed.

[0021]

As described above, the present invention adds a parity bit by performing error detection by comparing data after passing through the elastic store bit by bit with reference data bit by bit. No extra bits are required, and an error can be reliably detected even for errors of a plurality of bits.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of an error monitoring circuit in a device according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a specific configuration example of an in-device error monitoring circuit according to one embodiment of the present invention;

FIG. 3 is a block diagram showing a configuration of a conventional in-device error monitoring circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Write data 2 Write control pulse 3 Write clock 4 Elastic store 5 Read data 6 Read control path 7 Read clock 8 Delay amount detection circuit 9 PLO monitoring circuit 10 Variable delay circuit 11 Delay amount information 12 PLO stable / unstable operation information 13 Delayed data 14 Data comparison circuit 15 Data error raw information 16 Output control circuit 17 Data error information 18 Parity calculation addition circuit 19 Parity error detection circuit 20 PLO 21 Delay amount calculation circuit 22 Write-side frame counter 23 Read-side frame counter 24 Slip detection circuit 25 Flip-flop 26 Flip-flop 27 Match detection circuit 28 OR circuit 29 Mismatch information

Claims (1)

(57) [Claims] A write data is controlled by a write control pulse and input by a write clock, read data is controlled by a read control pulse and output by a read clock, and the write clock and the read clock are frequency synchronized by a PLO. Data writing / reading means, a delay amount detecting means for detecting a delay time from writing to reading of data in the data writing / reading means, and monitoring the write control pulse and the read control pulse and controlling the PLO. PLO monitoring means for outputting stable / unstable operation information, variable delay means for inputting the write data and providing a delay of the delay time, and outputting data of the variable delay means and the read data one bit at a time. Compare and check for matches and mismatches. Data comparison means for outputting data error information, and output control means for receiving the stable / unstable operation information of the PLO and outputting the data error information from the data comparison means only when stable operation information is input. In-device error monitoring circuit.