JPH10233765A - Phase matching system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the phase matching system of two digital transmission lines configured simply at a low cost without the need of insertion of any multi- frame synchronization pattern by a transmitter side. SOLUTION: Memories 4A, 4B for both data A, B are read by a common read pulse S generated from a delay detection and read pulse generator 3 based on frame synchronization pulses of the data A, B of transmission lines A, B. Data AA are shifted by a multi-frame shift circuit 6, comparators 7A-7A+1 are used to compare the data AA with other BB and a decoder 8 decodes coincidence/dissidence to obtain data outputs AOUT, BOUT whose phases are matched.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase matching system, and more particularly, to a phase matching system in a case where a transmission line is switched between devices connected by a plurality of digital transmission lines, for example, from an active system to a standby system without a momentary interruption. About.

[0002]

2. Description of the Related Art With the recent spread of digital technology including computer technology, it is necessary to mutually transmit and receive digital data (hereinafter referred to as transmission) by connecting two mutually separated digital devices via a transmission line. . Moreover, since these digital devices or devices operate in close relation to each other, they are connected by a plurality of transmission lines. When a failure or the like occurs in the plurality of transmission paths (working transmission paths), the transmission path is immediately (ie, without instantaneous interruption) switched to another transmission path (standby transmission path) to secure the transmission path, that is, between the two digital devices. Must maintain normal operation.

However, it is impossible for the working transmission line and the protection transmission line to be physically (or electrically) identical, and there is an unavoidable delay between the two transmission lines. Therefore, in order to switch from the working transmission line to the protection transmission line or vice versa, it is necessary to adjust the data delay amounts of both transmission lines.

[0004] A conventional hitless switching method for switching transmission paths without hitting the data in accordance with the amount of data delay is disclosed in, for example, JP-A-6-350579. The hitless switching method or the phase matching method disclosed in this publication,
The transmitting side inserts a plurality of multi-frame synchronization patterns every other multi-frames, while the receiving side performs multi-frame synchronization pull-in on the plurality of multi-frames set on the transmitting side to detect delay amounts of a plurality of systems. Next, data is stored in a buffer memory having a multi-frame capacity provided for each system, and is output from the buffer memory in accordance with the system having the largest delay amount, thereby expanding the phase matching range of multiple frames or more. Here, the detection of the delay amount depends on the synchronization of a plurality of multiframes. The amount of data stored in the buffer memory corresponds to the maximum multi-frame amount.

[0005]

In the above-described conventional phase matching method, it is necessary to insert a predetermined bit pattern sequence that is repeated in a plurality of multiframes on the transmitting side. However, there is a disadvantage that the circuit scale becomes large because a plurality of multi-frame synchronization pull-in operations are performed using the bit pattern extracted from the above. Further, since a buffer memory having a large memory capacity is used, there is a disadvantage that the buffer memory becomes expensive and power consumption increases.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a phase matching method which makes it unnecessary to insert a multi-frame synchronization pattern on the transmission side, does not increase the circuit scale, and reduces power consumption. .

[0007]

In order to solve the above-mentioned problems, a phase matching system according to the present invention employs two transmission lines A,
In the phase matching method for matching the phases of digital data A and B transmitted through B, one selected data A is shifted by (1 to M + 1) multi-frames, and each frame-shifted data is shifted to the other data B And a match / mismatch is detected by comparing with the data A that matches in the comparison.
And outputs the predetermined frame delay data and the data B.

[0008] Here, the comparison is performed by determining that a match occurs at any frame shift point between X (positive integer) multi-frames, and determining that the data A and the data B do not match by the comparison operation. And the same comparison operation is performed. The data A and B to be compared are:
The input data is stored in the memories A and B, respectively, and is performed based on the output data obtained by reading the data in the memories A and B with the common read pulse delayed by the delay amount of the frame synchronization pulse of the re-input data, The read pulse is a delayed read pulse obtained by adding a fixed value to the delay amount of the re-input data.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a preferred embodiment of a phase matching system according to the present invention will be described with reference to the drawings. FIG.
FIG. 2 is a configuration diagram of a preferred embodiment for realizing the phase matching method of the present invention. In this phase matching method, it is assumed that data A from a transmission path A (for example, a working transmission path) and data B from a transmission path B (for example, a protection transmission path) are input. These data A and B are input to the frame synchronization detecting circuits 1A and 1B, respectively,
Are detected. The frame synchronization pulse a detected by each of the frame synchronization detection circuits 1A and 1B,
The head of b, ie, the rising point, is detected by the frame head position detection circuits 2A and 2B.

Next, a delay time detection and pulse generation circuit 3
Detects the delay time α between the pulses a and b and adds the fixed delay time β to generate the pulse S.
The data A and B from the circuits 2A and 2B are input to the memory blocks 4A and 4B, respectively, and are sequentially stored at predetermined memory addresses.

The digital data A and B stored in the memory blocks 4A and 4B are sequentially read using the output pulse S of the pulse generation circuit 3 as a read pulse, and the data A
A and data BB are output. The data AA and BB are input to both of the selectors 5A and 5B, so that either the data AA or BB can be output from the selector 5A by the selection of the operator, and the data BB is also output from the selector 5B.
Or AA is output.

The output of the selector 5A is supplied to comparators 7A and 7A.
B,... 7M + 1 and input to the output selectors 9A, 9B. The output of the selector 5B is input to the (1 to M + 1) frame shift circuit 6, and a multi-frame shift signal of 1 to M + 1 frames is output. These (1 to
M + 1) The frame shift data is output from the comparators 7A to 7A, respectively.
Input to M + 1. The comparison outputs of the comparators 7A to 7M + 1 are input to the decoded value generator 8. The output of the decode value generator 8 is input to output selectors 9A and 9B,
It outputs data A and data B, respectively. In addition, for the reason described later, in order to control the selectors 5A, 5B and 9A, 9B, the output of the decode value generator 8
9 is input.

Next, the operation of the phase matching device shown in FIG. 1 will be described in detail with reference to FIGS. FIG. 2 shows FIG.
3 is a time chart for explaining the operation of each part of the phase matching device shown in FIG. 3, and FIG. 3 is an operation flowchart of the phase matching device shown in FIG.

In the time chart of FIG. 2, (1) and (2) indicate the frame synchronization pattern detection circuit 1 of FIG.
Data A and data B input to A and 1B.
(3) and (4) are a pulse a and a pulse b output from the circuits 2A and 2B of FIG. 1 to the delay amount detecting and reading pulse generator 3, respectively. (5) is a read pulse S output by the pulse generator 3 for reading the memory blocks 4A and 4B, and a fixed delay amount β is added to the delay amount (time) α from the pulse a to the pulse b (α + β) ) And output in response to the pulse a.

(6) and (7) are data AA and data BB read out from the memory blocks 4A and 4B of FIG. (8), (9) and (10)
The data AA or BB shifted by the multi-frame shift circuit 6 of FIG.
Frame shift data and (M + 1) frame shift data. Here, the data output from the multi-frame shift circuit 6 is the data AA according to the setting of the selector 5B.
Alternatively, one of the data BB is selected. The time chart of FIG. 2 shows a case where the data AA is selected by the selector 5B for convenience.

(11), (12) and (13) correspond to FIG.
7A, 7B, 7M + 1 (or COMP1, COMP2,
COMP (M + 1)). (14) is a decode value of the decode value generator 8. Finally, (15) and (16) show the data AOUT and data BOUT output from the output selectors 9A and 9B of FIG. In this example, since the comparator 7B generates a coincidence output, (5) is 2
The frame shift data is data AOUT. Thereby, both output data A and B are completely phase-matched.

Next, the operation procedure of this embodiment will be described with reference to the flowchart of FIG. This flowchart is similar to the block diagram of FIG. 1 and can be easily understood by those skilled in the art. When the phase matching operation is started at a start 10, the transmission paths A and B are respectively transmitted at blocks 11A and 11B.
Frame synchronization is detected. Blocks 12A and 12B detect the frame head positions a and b in the data A and B, respectively. In block 13, the delay amount α to the head position b of the data B is detected based on the head position a of the data A,
By adding the fixed value β (α + β), the memory block 4A,
Readout position C of 4B, that is, in the time chart of FIG.
The pulse S of (5) is generated.

In blocks 14A and 14B, data A and B are stored in respective memory blocks 4 based on a and b, respectively.
A and 4B are sequentially stored or stored. Next, block 15
In A and 15B, data A and B in the memory blocks 4A and 4B are read based on the common read pulse S generated in the block 13, respectively.
Data AA and data BB shown in (6) and (7) are output.

In block 16, the data AA obtained in block 15A is shifted by (1 to M + 1) multi-frames to obtain one frame shift data to (M + 1) frame shift data. Multi-frame data comparison is performed in blocks 17A to 17M + 1. In block 18, the comparison results in blocks 17A to 17M + 1 are decoded and X
If they match in a succession of multi-frames, the decoding value amount is recognized as being delayed by a frame and output. In that case, the process proceeds to block 19, and the phase matching operation is completed.
If the decoded value is 0, it is determined that the delay of the transmission path B is larger than that of the transmission path A, and the input to the shift register, which is the multi-frame shift circuit 6 in FIG.

This switching is performed by a selector or a switch (SW).
Is performed in blocks 20A and 20B. As described above, the data A and the data B are switched, and the blocks 21, 22A to 22M + 1 and 23 are used to perform the above-described block 16,
The same comparison operation as that of 17A to 17M + 1 and 18 is performed. In block 23, the comparison result is decoded, and when the results match for consecutive X multiframes, the decoding value amount is recognized as being delayed by the frame and output. In this case,
The process proceeds to block 19 to complete the phase matching operation. If the decode value is 0, the transmission path A recognizes that an abnormality has occurred in the transmission path B, and proceeds to block 24 to display the transmission path abnormality or issue an alarm.

As will be understood from the above description, the present invention can reduce the delay difference between data A and data B constituting a redundant system by using a large delay amount without adding a special bit pattern or the like in a digital transmission path. Phase adjustment is performed using the content of the other data. One data A is shifted by a multi-frame length in frame units, and is compared with the other data B in each frame unit. If any frame shift point coincides between X (positive integers of 1, 2, 3,...) Multiframes, it is recognized that phase matching has been completed. If there is no match between the X multiframes, the same operation is performed with the data A and data B interchanged. If there is no match between the X multiframes at any of the frame points, it is recognized that there is an abnormality in the transmission path, and a transmission path abnormality is output.

The preferred embodiment of the phase matching method of the present invention has been described above. However, the present invention is not limited to the specific embodiment, and various modifications can be made in accordance with the specific application. Those skilled in the art will readily appreciate that there are. Therefore, the present invention includes such modifications.

[0023]

As described above, according to the phase matching method of the present invention, it is not necessary to insert a multi-frame synchronization pattern on the transmitting side. In addition, since the phase is adjusted for each frame and the phase is adjusted to data having a large delay amount with reference to the data of one of the transmission paths, the circuit scale can be reduced. Further, since the multi-frame synchronization pull-in is performed by the data itself, the time required for the synchronization pull-in can be reduced. Furthermore, since one frame memory amount is used, the memory capacity can be reduced, and power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a preferred embodiment of a phase matching system according to the present invention.

FIG. 2 is a time chart for explaining the operation of each component of the phase matching method of FIG. 1;

FIG. 3 is a flowchart showing an operation procedure of an embodiment of a phase matching method according to the present invention.

[Explanation of symbols]

 3 Delay detection and readout pulse generator 5A, 5B, 9A, 9B Selector 6 Multi-frame shift circuit 7A,... 7M + 1 Comparator 8 Decode value generator

Claims (5)

[Claims] In a phase matching method for matching the phases of digital data A and B transmitted via two transmission paths A and B, one selected data A is shifted by (1 to M + 1) multiframes, Each frame-shifted data is compared with the other data B to detect a match or mismatch,
A phase matching method, comprising outputting predetermined frame delay data of the data A and the data B that match in the comparison. 2. The phase matching method according to claim 1, wherein the comparison is determined to be a match when any frame shift point matches between X (positive integer) multiframes. 3. The method according to claim 1, wherein when the comparison operation determines that there is a mismatch.
3. The phase matching method according to claim 1, wherein the same comparison operation is performed by switching between the data A and the data B. 4. The data A and B to be compared are obtained by accumulating input data in memories A and B, respectively, and using a common read pulse delayed by a delay amount of a frame synchronization pulse of re-input data. 2. The phase matching method according to claim 1, wherein the phase adjustment is performed based on output data obtained by reading the data of B. 5. The phase matching method according to claim 4, wherein said read pulse is a delayed read pulse obtained by adding a fixed value to said delay amount of said re-input data.