KR920004921B1

KR920004921B1 - Clock selection circuit

Info

Publication number: KR920004921B1
Application number: KR1019890013188A
Authority: KR
Inventors: 주범순; 이창문; 이정희; 김옥희
Original assignee: 한국전기 통신공사; 이해욱; 재단법인 한국전자통신연구소; 경상현
Priority date: 1989-09-12
Filing date: 1989-09-12
Publication date: 1992-06-22
Also published as: KR910007274A

Abstract

The circuit includes a TMR (triple modular redundancy) circuit (1) for receiving synchronizing clock codes to output selection information for normally operating synchronizing clocks. A clock receiving circuit (2) receives triplexed synchronizing clocks from a synchronizing clock generating section. A monitor circuit (3) monitors the state of the triplexed synchronizing clocks to output an information on it. A PROM (4) outputs code values for the synchronizing clocks, and a multiplexer (5) receives the triplexed synchronizing signals, and outputs the signals selected by the output values of the PROM (4). With the circuit, no separate clock selecting data is required.

Description

Clock selection circuit

제 1 도는 본 발명의 구성도.1 is a block diagram of the present invention.

제 2 도는 TMR 논리회로의 구성도.2 is a block diagram of a TMR logic circuit.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : TMR 논리회로 2 : 클럭 수신회로1: TMR logic circuit 2: clock receiving circuit

3 : 모니터 회로 4 : PROM(Programmable Read Only Memory)3: monitor circuit 4: PROM (Programmable Read Only Memory)

5 : 멀티플렉서5: multiplexer

본 발명은 TMR 논리회로의 결과를 이용하여 클럭을 선택하기 위한 클럭선택회로에 관한 것이다.The present invention relates to a clock selection circuit for selecting a clock using the result of a TMR logic circuit.

TMR 논리회로는 전자교환기의 망동기 장치에 있어서, 신뢰도를 향상시키기 위해 동기 클럭 발생부로부터의 동기 클럭이 3중화된 경우, 3중화된 동기 클럭을 받아들여 정상적인 동기 클럭을 선택하기 위한 선택정보를 제공하는 회로이다.The TMR logic circuit selects a selection information for receiving a triplexed synchronous clock and selecting a normal synchronous clock when the synchronous clock from the synchronous clock generator is tripled in order to improve reliability. It is a circuit to provide.

본 발명의 목적은 TMR(Triple Modular Readundancy) 논리회로의 결과와 입력 클럭 모니터 값을 PROM의 입력으로 하여 PROM의 출력으로 클럭을 선택하는 클럭선택회로를 제공하는데 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a clock selection circuit that selects a clock as an output of a PROM by using a result of a TMR (Triple Modular Readundancy) logic circuit and an input clock monitor value as an input of a PROM.

본 발명은 상기 목적을 달성하기 위해, 3중화된 클럭을 받아들여 정상적인 동기 클럭을 선택하기 위한 선택정보를 발생하는 TMR(Triple Modular redundancy) 논리회로, 3중화된 클럭을 수신하는 클럭수신회로, 상기 클럭수신로에 연결되어 수신된 클럭을 모니터하는 모니터 회로, 상기 TMR 논리회로와 모니터 회로에 연결되어 상기 모니터 회로의 제어에 의해 클럭을 선택하는 PROM, 및 상기 PROM과 클럭수신회로에 연결되어 선택된 클럭을 출력하는 멀티플렉서로 구성되어 있다.In order to achieve the above object, the present invention provides a triple modular redundancy (TMR) logic circuit that receives a tripled clock and generates selection information for selecting a normal synchronous clock, a clock receiving circuit that receives a tripled clock, and A monitor circuit connected to a clock receiver for monitoring a received clock, a PROM connected to the TMR logic circuit and a monitor circuit to select a clock under control of the monitor circuit, and a clock selected to be connected to the PROM and a clock receiver circuit It consists of a multiplexer that outputs.

이하, 첨부된 도면을 참조하여 본 발명의 일실시예를 상세히 설명하면 다음과 같다.Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

제 1 도는 본 발명의 구성도이고, 제 2 도는 TMR 논리회로의 구성도이다.1 is a block diagram of the present invention, and FIG. 2 is a block diagram of a TMR logic circuit.

제 1 도는 도시한 바와 같이 본 발명은, TMR 논리회로(10), 클럭수신회로(2), 모니터 회로(3), RPOM(4), 및 멀티플렉서(MUX)(5)로 구성되어 있다.As shown in FIG. 1, the present invention comprises a TMR logic circuit 10, a clock receiving circuit 2, a monitor circuit 3, an RPOM 4, and a multiplexer (MUX) 5. As shown in FIG.

도면을 참조하여 본 발명의 일실시예에 대한 구성 및 동작을 상세히 살펴보면 다음과 같다.Looking at the configuration and operation of the embodiment of the present invention in detail with reference to the drawings as follows.

소프트웨어가 프로세서(MGCP)를 통해 시스템에 써주는 동기클럭 코드값을 입력받아 논리적으로 분석하여 정상적으로 동작한다고 판단되는 동기클럭의 코드값을 출력하는 TMR논리회로(1), 외부의 동기 클럭 발생부(도면에 도시하지 않았음)로부터 3중화된 동기클럭을 수신하는 클럭수신회로(2), 상기 클럭수신회로(2)에 연결되어 클럭 수신회로(2)에서 수신한 3개 동기클럭의 상태를 감시하여 그 상태에 대한 정보를 출력하는 모니터 회로(3), 상기 TMR 논리회로(1)와 상기 클럭수신회로(2)에 연결되어 상기 TMR 논리회로(1)에서 출력된 동기클럭 코드값과 상기 모니터 회로(3)에서 출력된 동기클럭 상태정보를 조합하여 동기클럭의 하드웨어적인 상태와, 소프트웨어가 프로세서를 통해 시스템에 써주는 동기클럭 코드값의 상태가 가장 정상적이라 판단되는 동기클럭에 대한 코트값(S0,S1)을 출력하는 PROM(4), 및 상기 클럭수신회로(2)와 상기 PROM(4)에 연결되어 상기 클럭 수신회로(2)에서 수신하여 출력하는 3개의 동기클럭을 입력으로 하고 상기 PROM(4)의 출력(S0,S1)을 제어신호로 받아 동기클럭을 선택하여 출력하는 멀티플렉서(5)로 구성된다.TMR logic circuit 1 for receiving the synchronous clock code value that the software writes to the system through the processor (MGCP) and logically analyzing and outputting the code value of the synchronous clock which is determined to operate normally, and an external synchronous clock generator ( (Not shown in the figure) connected to the clock receiving circuit (2) and the clock receiving circuit (2) for receiving the triplexed synchronous clock, and monitoring the state of the three synchronous clocks received by the clock receiving circuit (2). A monitor circuit (3) for outputting information on the state, and a synchronous clock code value and the monitor output from the TMR logic circuit (1) connected to the TMR logic circuit (1) and the clock receiving circuit (2). A synchronization clock in which the hardware state of the synchronous clock and the state of the synchronous clock code value that the software writes to the system through the processor by combining the synchronous clock state information output from the circuit 3 are judged to be the most normal. PROM 4 for outputting the coat values S0 and S1 for the clock, and three synchronization signals connected to the clock receiving circuit 2 and the PROM 4 and received and output by the clock receiving circuit 2. It consists of a multiplexer 5 which takes a clock as an input and receives outputs S0 and S1 of the PROM 4 as a control signal and selects and outputs a synchronous clock.

또한, 상기 TMR 논리회로(1)가 상기 PROM(4)으로 보내는 동기 클럭 코드값은 2비트이며, 상기 코드값은 외부의 동기 클럭발생부에서 전송되는데 전송시에는 리던던시(Redundancy)를 주기위해 패리티 비트를 포함한 3비트로 전송된다. 이것은 상기 TMR 논리회로(1)에서 출력되는 동기클럭 코드값의 신뢰도를 높이게 하기 위함이다.In addition, the synchronous clock code value transmitted from the TMR logic circuit 1 to the PROM 4 is 2 bits, and the code value is transmitted from an external synchronous clock generator, and parity is used to provide redundancy during transmission. It is transmitted in 3 bits including the bits. This is to increase the reliability of the sync clock code value output from the TMR logic circuit 1.

여기서 TMR 논리회로(1)의 일실시예를 제 2 도를 참조하여 설명하기로 한다.An embodiment of the TMR logic circuit 1 will now be described with reference to FIG.

제 2 도에서 TMR 논리회로(1)는 래치회로(21, 25, 29), 멀티플렉서(22, 26, 30), 가산기(23, 27, 31, 32), 및 모니터(24, 28, 33)로 구성되어 있다.In FIG. 2, the TMR logic circuit 1 includes latch circuits 21, 25, 29, multiplexers 22, 26, 30, adders 23, 27, 31, 32, and monitors 24, 28, 33. Consists of

래치회로(21, 25, 29)는 동기 클럭 발생부의 프로세서(MGCP)에서 오는 3개의 선택 정보값(이하 MCC라함)을 입력으로 하고, 쓰기 인에이블 신호(WR0, WR1, WR2)를 입력하여 MCC를 래치한다.The latch circuits 21, 25, and 29 input three selection information values (hereinafter referred to as MCCs) from the processor MGCP of the synchronous clock generator, and input write enable signals WR0, WR1, and WR2 to MCC. Latch.

멀티플렉서(MUX)(22, 26, 30)는 래치회로(21, 25, 29)로부터 출력된 세출력중 두 개의 출력을 선택하여 각각 입력으로 하고 모니터회로(24, 28, 33)로부터의 출력을 선택단자(S)로 받아들여 모니터회로(24, 28, 33)의 제어에 의해 각각 세출력(10, 11, 12)을 출력한다.The multiplexer (MUX) 22, 26, 30 selects two outputs among the three outputs output from the latch circuits 21, 25, and 29 as inputs, respectively, and outputs the outputs from the monitor circuits 24, 28, 33. It accepts by the selection terminal S, and outputs the three outputs 10, 11, 12 respectively by control of the monitor circuits 24, 28, and 33. As shown in FIG.

가산기(23, 27, 31)는 상기 멀티플렉서(22, 26, 30)의 출력중 각각 하나씩을 선택하여 입력하고 입력신호를 가산하여 선택신호(S0,S1,S2)를 출력하며, 이중 선택신호(S0, S2)은 클럭선택회로로, 선택신호(S0, S1, S2)는 다시 가산기(32)로 출력된다.The adders 23, 27, and 31 select and input each one of the outputs of the multiplexers 22, 26, and 30, add the input signals, and output the selection signals S0, S1, and S2. S0 and S2 are clock selection circuits, and the selection signals S0, S1 and S2 are outputted to the adder 32 again.

가산기(32)는 이러한 3개의 선택신호(S0, S1, S2)를 받아들여 가산한후 그 결과를 TMR 장애감지회로로 보낸다.The adder 32 receives and adds these three selection signals S0, S1, and S2, and sends the result to the TMR failure detection circuit.

여기서 클럭선택신호(S0, S1)는 본 발명에서 마스터 코드 데이타로 사용되며, 제 1 도의 PROM(4)으로 전송된다.The clock selection signals S0 and S1 are used as master code data in the present invention, and are transmitted to the PROM 4 of FIG.

본 발명은 상기와 같이 구성되어 3중화된 시스템에서 클럭을 선택함에 있어 입력클럭을 모니터한 값과 TMR 논리회로에서 나온 결과로 PROM의 출력을 제어함으로써 소프트웨어가 별도로 클럭 선택용으로 데이타를 써주지 않아도 되며 PROM을 사용함으로써 회로를 간단화시킬 수 있다.The present invention is configured as described above in controlling the output of the PROM as a result of monitoring the input clock and the result of the TMR logic in the clock selection in the triple system, so that software does not have to write data for clock selection separately. The circuit can be simplified by using PROM.

Claims

TMR logic circuit (1), which receives the synchronous clock code value that the software writes to the system through the processor (MGCP) and logically analyzes it to generate the selection information of the synchronous clock determined to operate normally, from an external synchronous clock generator A clock receiving circuit (2) for receiving a tripled synchronous clock, and connected to the clock receiving circuit (2) to monitor the status of the three synchronous clocks received by the clock receiving circuit (2) and output information on the status A synchronous clock code value output from the TMR logic circuit 1 and a synchronous clock output from the monitor circuit 3, which are connected to the monitor circuit 3, the TMR logic circuit 1 and the monitor circuit 3 Code values (S0, S1) for the synchronous clock where the hardware state of the synchronous clock and the state of the synchronous clock code value that the software writes to the system through the processor are the most normal by combining the state information. PROM 4 to be output, and three synchronization clocks connected to the PROM 4 and the clock receiving circuit 2 to be received and output by the clock receiving circuit 2 as inputs. And a multiplexer (5) for receiving outputs (S0, S1) as control signals and outputting a selected clock.

The TMR logic circuit (1) according to claim 1, wherein the TMR logic circuit (1) is transmitted and input to the TMR logic circuit (1) in order to increase the reliability of a synchronization clock selected by a 2-bit code value output from the TMR logic circuit (1) to the PROM (4). And a code value of the synchronous clock is composed of three bits including a parity bit for providing redundancy in addition to the code value of the two bits.