JP2874444B2 - Line monitoring circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a line monitoring circuit,
In particular, the present invention relates to a line monitoring circuit that monitors a line status online.

[0002]

2. Description of the Related Art FIG. 4 shows a conventional example. In the conventional example of FIG. 4, a first pulse generation circuit 252 for outputting various pulses is provided.
And an empty time slot at a fixed position in a frame of the input data signal 51 in synchronization with the path pattern load pulse signal 52 from the second pulse generation circuit 256 and the first pulse generation circuit 252. A path pattern insertion circuit 251 for inserting a changed path pattern, a monitored object 253 for delaying the data signal 53 from the path pattern insertion circuit 251 in synchronization with a pulse signal from the first pulse generation circuit 252, and a second pulse generation circuit 25
6, a path pattern latch circuit 254 that separates a path pattern from the output data signal 54 of the monitored object 253 in synchronization with the path pattern latch signal 55 from the monitoring target 253, and a comparison pulse signal 57 from the second pulse generation circuit 256. A comparison circuit 255 is provided, which compares the path pattern signal 56 from the path pattern latch circuit 254 with a preset path pattern and outputs an alarm signal 218 if the result does not match.

Here, the operation of the above conventional example will be described.

[0004] The path pattern insertion circuit 251 is set in advance to an empty time slot at a fixed position in the frame of the input data signal 51 in synchronization with the path pattern load pulse signal 52 input from the first pulse generation circuit 252. The inserted path pattern is output to the monitored object 203.

[0005] The monitored object 253 inputs and delays the data signal 53 from the pass pattern insertion circuit 251 in synchronization with the pulse signal input from the first pulse generation circuit 252.

[0006] The pass pattern latch circuit 254 is connected to the second
Pass pattern latch signal 5 from the pulse generation circuit 256 of FIG.
5, a path pattern is separated from the output data signal 54 of the monitored object 253, and the separated path pattern is output to the comparison circuit 255 as the path pattern signal 26.

[0007] The comparison circuit 255 synchronizes the comparison pulse signal 57 input from the second pulse generation circuit 256 with the path pattern signal 5 from the path pattern latch circuit 254.
6 and compares it with a preset pass pattern. If the comparison results in a mismatch, an alarm signal 28 is output.
Is output.

[0008]

However, in the above-mentioned conventional example, since a preset path pattern is inserted into an empty time slot at a fixed position in a frame of an input data signal, the insertion of a path pattern is not performed. There is a disadvantage that it is not possible to monitor an actual data error existing at a time different from the time when the data error occurs.

[0009]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a line monitoring circuit which can overcome the disadvantages of the prior art and, in particular, can provide direct online monitoring of all time slot data in a frame with actual data contents. It is in.

[0010]

Therefore, according to the present invention, there is provided an address generating circuit for outputting an address value of a time slot to be monitored in an input data signal, and an input data signal corresponding to an address value from the address generating circuit. Check data creating means for transferring data of the time slot to an empty time slot, writing a predetermined path pattern in the time slot, and outputting the data to the monitored object. Further, a path pattern comparing means for extracting a path pattern from the output data signal of the monitored object and outputting an alarm signal if the path pattern does not match a predetermined path pattern, and converting the output data signal of the monitored object into the original input data signal An input data restoring means for restoring is provided. This aims to achieve the above-mentioned object.

[0011]

The check data creating means separates the data of the time slot in the input data signal designated by the address value from the address generating circuit, delays the data by one frame, and inserts the separated data into an empty time slot. . Further, the check data creation means inserts a predetermined pass pattern into a time slot of the input data signal specified by the address value from the address generation circuit, and converts the address value indicated by the output of the address generation circuit into an empty time slot. Write and output to the monitored object.

The path pattern comparing means extracts an address value written in the output data to be monitored, and extracts a path pattern written in a time slot corresponding to the address value. Then, a comparison is made with a preset pass pattern, and an alarm signal is issued if the comparison result does not match.

The input data restoring means separates the save data from the output data to be monitored, separates the path pattern of the time slot corresponding to the address value from the path pattern comparing means, and stores the separated data in the time slot. Send.

Further, by changing the address value in the address generating circuit for each frame, it is possible to directly monitor all the time slot data in the frame with the actual data contents.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

The embodiment shown in FIG. 1 includes an address generation circuit 102 for outputting an address value of a time slot to be monitored in an input data signal 1, and an address generation circuit 10
Check data generating means 100A for transferring the data of the time slot in the input data signal 1 corresponding to the address value from 2 to an empty time slot, writing a predetermined path pattern in the time slot, and outputting to the monitored object 107 A path pattern comparing means 100B for extracting a path pattern from the output data signal of the monitored object 107 and outputting an alarm signal when the path pattern does not match a predetermined path pattern, and converting the output data signal of the monitored object 107 into the original input data. And input data restoring means 100C for restoring the signal.

Here, the pulse signal is supplied to the address generating circuit 102, the check data generating means 100A, the first pulse generating circuit 101 for supplying a pulse signal to the monitored object 107, the pass pattern comparing means 100B and the input data restoring means 100C. A second pulse generating circuit 108 for supplying is provided.

The check data creating means 100A
A data latch circuit 103 for separating data corresponding to the address value from the address generation circuit 102 from the input data signal 1 in synchronization with the first data latch pulse signal 3 from the first pulse generation circuit 101; Save data for delaying the data signal from the latch circuit 103 by one frame and storing the data separated by the data latch circuit 103 in an empty slot in synchronization with the data load pulse signal 4 from the first pulse generation circuit 101 An insertion circuit 104, a pass pattern insertion circuit 105 for saving data in synchronization with the pass pattern insertion pulse signal 5 from the first pulse generation circuit 101 and inserting a pass pattern into an empty time slot, and a first pulse generation circuit 10
An address insertion circuit 106 writes an address value indicated by the output of the address generation circuit 102 to an empty time slot and outputs the address value to the monitored object 107 in synchronization with the address write pulse signal 6 from 1.

Further, the pass pattern comparing means 100B
An address latch circuit 10 for detecting an address value written to the output of the monitored object 107 in synchronization with the address latch pulse signal 7 from the second pulse generation circuit 108
9 and the path pattern written in the time slot of the address value indicated by the output of the address latch circuit 109 from the output of the monitored object 107 in synchronization with the path pattern latch pulse signal 8 from the second pulse generation circuit 108 And a pass pattern check circuit 110 for comparing with a preset pass pattern and outputting an alarm signal 9 when they do not match.

The input data restoring means 100C includes a data latch circuit 111 for separating data from the output of the monitored object 107 in synchronization with the second data latch pulse signal 10 from the second pulse generating circuit 108; From the output of the monitored object 107 in synchronization with the data multiplexed pulse signal 11 from the pulse generation circuit 108 of FIG.
And a data multiplexing circuit 112 for separating the path pattern of the time slot having the address value indicated by the output and multiplexing and transmitting the data separated by the data latch circuit 111 to the time slot.

Next, the operation of this embodiment will be described.
Here, the input data signal 1 is a. The signal a has a frame structure divided into nine time slots t1 to t9 as shown in FIG.
t2 is an empty time slot, t3 is frame data A, t4 is frame data B, t5 is frame data C, t6 is frame data D, t7 is frame data E, and t8 is frame data. Is the frame data F,
It is assumed that the frame data G is input at t9.

The address generating circuit 102 receives the address load pulse signal 2 from the first pulse generating circuit 101.
The case where "4" is output as the address value as shown in the output b in FIG.

[0023] The data latch circuit 103 synchronizes with the first data latch pulse signal 3 from the first pulse generation circuit 101 and outputs the input data signal 1 based on the address value “4” which is the output b of the address generation circuit 102. Of 4
The data “B” in the time slot t4 is separated from the input data signal 1 and output to the save data insertion circuit 104.

[0024] When the output c of the data latch circuit 103 is input, the save data insertion circuit 104 delays by one frame. Here, the time slot t before the delay
1 to t9 correspond to the time slots t1 'to t9' after the delay.

Further, the save data insertion circuit 104 has the first
In synchronization with the data load pulse signal 4 from the pulse generation circuit 101, the separated data "B" is inserted into the time slot t2 'corresponding to the empty time slot t2 of the input data signal 1, and is output to the pass pattern insertion circuit 105. I do.

[0026] When the output d of the save data insertion circuit 104 is input, the pass pattern insertion circuit 105 saves the data in synchronization with the pass pattern insertion pulse signal 5 from the first pulse generation circuit 101, and sets the time slot that is an empty time slot. At t4 ', a predetermined path pattern "P" is inserted, and the address insertion circuit 10
6 is output.

[0027] When the output e of the pass pattern insertion circuit 105 is input, the address insertion circuit 106 synchronizes with the address write pulse signal 6 from the first pulse generation circuit 101 and outputs the address value “4” indicated by the output b of the address generation circuit 102. Into the empty time slot t1 ′,
Output to the monitored object 107.

[0028] The monitored object 107 delays the output f of the address insertion circuit 106, and
9 is output. Here, the time slots t1 'to t9' of the output f of the address insertion circuit 106 are the time slots r1 of the output g of the monitored object 107 as shown in FIG.
~ R9.

[0029] The address latch circuit 109 detects the address value “4” written in the time slot r1 of the output g of the monitored object 107 in synchronization with the address latch pulse signal 7 from the second pulse generation circuit 108, Path pattern check circuit 110 and data multiplexing circuit 1
12 is output.

[0030] When the output h of the address latch circuit 109 is input, the pass pattern check circuit 110 synchronizes with the pass pattern latch pulse signal 8 from the second pulse generation circuit 108 and outputs the address latch circuit Address value “4” indicated by output h of 109
Is detected in the time slot r4 corresponding to the path pattern “P”. Then, a comparison with a predetermined pass pattern is performed, and if the comparison result does not match, an alarm signal 9 is issued.

[0031] The data latch circuit 111 separates the data “B” of the time slot r2 from the output g of the monitored object 107 in synchronization with the second data latch pulse signal 10 from the second pulse generation circuit 108, and performs data multiplexing. Output to the circuit 112.

[0032] The data multiplexing circuit 112 synchronizes with the data multiplexed pulse signal 11 from the second pulse generation circuit 108 to correspond to the address value “4” indicated by the output h of the monitored object 107 to the output h of the address latch circuit 109. The data “B” separated by the data latch circuit 111 is multiplexed and transmitted to the time slot r4.

Further, by changing the address value on a frame-by-frame basis by the address generating circuit 102, direct online monitoring can be performed for all the time slot data in the frame with the actual data contents.

[0034]

Since the present invention is constructed and functions as described above, according to the present invention, it is possible to specify a time slot in the input data to be monitored in the frame. In addition, it is possible to provide an unprecedented excellent line monitoring circuit capable of performing online monitoring with actual data contents.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of the present invention.

FIGS. 2 and 3 are timing charts for explaining the operation of the embodiment of FIG.

FIG. 4 is a configuration diagram showing a conventional example.

[Explanation of symbols]

 1: input data signal 2: address load pulse signal 3: first data latch pulse signal 4: data load pulse signal 5: pass pattern insertion pulse signal 6: address write pulse signal 7: address latch pulse signal 8: pass pattern latch pulse Signal 9: Alarm signal 10: Second data latch pulse signal 11: Data multiplex pulse signal 100A: Check data creation means 100B: Pass pattern comparison means 100C: Input data restoration means 101: First pulse generation circuit 102: Address generation circuit 103: data latch circuit 104: save data insertion circuit 105: pass pattern insertion circuit 106: address insertion circuit 107: monitored object 108: second pulse generation circuit 109: address latch circuit 110: path pattern check circuit 111: data Latch circuit 112: a data multiplexing circuit

Claims (2)

(57) [Claims] 1. An address generating circuit for outputting an address value of a time slot to be monitored in an input data signal, and the data of the time slot in the input data signal corresponding to the address value from the address generating circuit is set as an empty time slot. And a check data creating means for writing a predetermined path pattern in the time slot and outputting the same to the monitored object at the same time, and extracting a path pattern from the output data signal of the monitored object to find a mismatch with the predetermined path pattern. A line monitoring circuit comprising: a path pattern comparing unit that outputs an alarm signal in the case; and an input data restoring unit that restores a monitored output data signal to an original input data signal. 2. A data latch circuit for separating data corresponding to an address value from the address generation circuit from an input data signal, and a delay of the data signal from the data latch circuit by one frame. A save data insertion circuit for storing data separated by the data latch circuit in an empty slot, a pass pattern insertion circuit for saving data and inserting a pass pattern in an empty time slot, and an address indicated by an output of the address generation circuit. 2. The line monitoring circuit according to claim 1, further comprising an address insertion circuit for writing a value to an empty time slot and outputting the value to a monitored object.