JPH08316944A - Phase adjustment circuit - Google Patents

Abstract

PURPOSE: To provide the phase adjustment circuit having a simple configuration which controls the phase delay of input data by external control data. CONSTITUTION: This adjustment circuit consists of a synchronous self-load counter 10 operated synchronously with an input clock 22, a latch circuit 12 which latches delay extent control data 20, a comparator 11 which compares output data 23 of the counter 10 and delay extent control data 20 with each other, and a FIFO memory 13. The extent of delay of an input data signal 26 is set by delay extent control data 20 and a delay extent control data latch signal 21; and when this set value coincides with counted data of the counter 10, the comparator 11 generates a comparison count signal 25 to input it to the FIFO memory 13 and resets counted data of the counter 10. Thus, the input data signal 26 is delayed in the FIFO memory 13 by the set extent of delay and is outputted to the outside as an output data signal 27.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for inspecting an electronic circuit board mounted on, for example, a transmission device, and more particularly, it delays a phase of an input data signal synchronized with a clock in a circuit to be inspected as appropriate. The present invention relates to a phase adjustment circuit that outputs a synchronized data signal.

[0002]

2. Description of the Related Art As a conventional phase adjusting circuit of this type, an input data signal synchronized with a clock is input to a multi-stage connection shift register which operates in synchronization with an input clock, and is input to an arbitrary output tap of the multi-stage shift register. There is known a configuration (hereinafter referred to as Conventional Example 1) that outputs a data signal having an arbitrary phase delay amount by connecting an output line. Also, a synchronous counter that operates in synchronization with the input clock, a static memory for delaying the input data signal, and a write-side signal generator that creates a write address and a write control signal by using the output of the synchronous counter. , Which uses a synchronous counter output and is composed of a read address and a read-side signal generator that creates a read control signal, and delays the phase of the output data signal by the difference between the write / read address values (hereinafter, the conventional Example 2) is also known.

[0003]

However, each conventional example has the following problems. In the case of Conventional Example 1,
Since an output data signal having an arbitrary phase delay amount is output by connecting the output line to an arbitrary output tap of the multi-stage shift register, the output line must be changed every time the phase delay amount is changed. Further, the circuit scale increases as the phase delay amount increases and the input / output data signal width increases. In the case of the conventional example 2, since the control signals are respectively generated by the signal generators on the write side and the read side, and the phase of the output data signal is delayed based on the address difference between the write / read addresses, a dedicated signal generator is used. Multiple circuits are required,
The circuit scale becomes large and complicated.

An object of the present invention is to solve the above problems,
An object of the present invention is to provide a phase adjustment circuit that can adjust the phase of input / output data by external control without changing the circuit and regardless of the adjustment amount.

[0005]

The phase adjusting circuit provided by the present invention compares the input delay amount data and the count data of the counter with a synchronous self-load counter for counting the number of clocks of an input clock. A comparator that generates a comparison result signal when both match and resets the count data of the counter with the comparison result signal, and captures input data at the input timing of one comparison result signal, and outputs the next comparison result signal. And a FIFO memory that outputs the input data at the input timing. When the input timing of the delay amount data becomes a problem, in addition to the above configuration, a latch circuit for temporarily holding the delay amount data and guiding the held delay amount data to the comparator at a predetermined timing is provided.

[0006]

According to the present invention, the output timing (phase delay amount) of the input data input to the FIFO memory is adjusted based on the comparison result between the count data of the synchronous self-load counter and the delay amount data externally input. That is, the number of clocks is counted by the counter, and the count data and the delay amount data are compared by the comparator. When the input timing of the delay amount data is a problem, the delay amount data is input to the comparator via the latch circuit. When the count data of the counter matches the delay amount data, a comparison result signal is generated,
This is input to, for example, the reset terminal of the FIFO memory and the reset terminal of the counter. As a result, the counter is reset and a new count is started. The comparator regenerates the comparison result signal when the new count data matches the delay amount data. Repeat this.
The FIFO memory takes in the input data at the input timing of a certain comparison result signal and outputs the input data at the input timing of the next comparison result signal. In this way, the phase delay amount of the input data is arbitrarily changed according to the delay amount data input from the outside.

[0007]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a configuration diagram of a phase adjustment circuit according to an embodiment of the present invention. This phase adjustment circuit includes a synchronous self-load counter 10, a comparator 11, and a latch circuit 12.
And a FIFO (first in first out) memory 13 as basic configurations.

The counter 10 operates in synchronization with the input clock 22, and the latch circuit 12 uses the latch signal 21 which is a timing signal for determining the latch timing to control the delay amount control data 20 (control data for determining the delay amount, The same shall apply hereinafter). Comparator 11
Is for generating a comparison result signal (reset pulse) 25 when the output data 23 of the counter 10 and the latch data 24 output from the latch circuit 12 are compared and coincident with each other.

The FIFO memory 13 delays data by the comparison result signal 25 input from the comparator 11 and the input clock 22. This FIFO memory 13
Is a general FIFO memory composed of input / output terminals for data input, data output, reset write input, reset read input, write enable input, read enable input, write clock input, and read clock input. Writing / reading can be executed when the input and read enable inputs are enabled, and the FIFO memory 1 can be executed by the reset write input and the reset read input.
The write address pointer and the read address point in 3 are reset to address 0 respectively. First write clock input after reset write, data input is FIFO
The data output is read from the address 0 at the first read reset input after the reset read input, which is written in the address 0 on the memory 13. When the reset write input and the reset read input are input at the same time, the input data is not read at the same time as the writing because of an internal delay due to the write / read operation. In this case, the data written at the time of the first reset input is read at the time of the next reset input.

In order to output the output data 27 with respect to the input data 26 in an arbitrary phase, in the present embodiment, the arbitrary delay amount x is preliminarily set by the delay amount control data 20.
Set to 2. Then, when the output data 24 of the latch circuit 12 and the output data 23 of the counter 10 match, a comparison result signal 25 is generated, and this is used as a write and read reset signal and an external load signal of the counter 10, The input data 26 is delayed by the delay amount x, and the
The output data 27 is output from the data output terminal of the O memory 13.

The latch circuit 12 is provided to prevent malfunction of the delay amount control data 20 input from the outside. Therefore, if the logic of the delay amount control data 20 does not change during operation, this is omitted. You can also do it.

Next, the operation of the phase adjustment circuit of this embodiment will be described with reference to FIG. FIG. 2 is a time chart when the delay amount x is “3”. To explain only the basic operation of this embodiment, the signal delay of the phase adjustment circuit, the setup time, the hold time, the signal line width (1 ~ N, 1
m), input / output signal line width (1 to k), FIFO memory 13
, The signal polarity, etc. are ignored. Also, the FIFO
The write enable input and the read enable input of the memory 13 are presumed to be used in the enabled state in this embodiment, so the description of FIG. 1 is omitted.

In this example, the delay amount control data 20 is set in advance.
The delay amount is held in the latch circuit 12 by the delay amount control data latch signal 21. The counter output 23 of the counter 10 that operates in synchronization with the input clock 22 and the latch circuit 1
The output data 24 of No. 2 is compared by the comparator 11, and when they match each other, that is, when the delay amount is “3”, the comparison result signal 25 (reset pulse) is generated and input to the FIFO memory 13. The FIFO memory 13 has a comparison result signal 25 (reset write, reset read) and an input clock 22 (write clock,
The AND condition with the read clock) is determined, and when the condition is satisfied, that is, when both are active, writing and reading of the input data signal 26 are performed. Then, the input data written one cycle before is output from the data output terminal. As a result, the phase of the input data is delayed by the delay amount "3" set by the delay amount control data 20, and is output to the outside in a transparent state.

As described above, in this embodiment, an arbitrary delay amount x is set from the outside, and this delay amount x is compared with the count data of the synchronous self-load counter 10 that operates in synchronization with the clock. , Comparison result signal 25 of arbitrary cycle
To generate the comparison result signal 25 and the FIFO memory 13
Since the delay amount of input / output data is controlled by using and, the output line is changed every time the phase delay amount is changed like a conventional circuit that requires a multi-stage shift register, or the phase delay amount is changed according to the phase delay amount. There is no need to change the circuit scale.

Further, since the FIFO memory 13 is used, the timing signal generator for generating the write signal / read signal unlike the conventional circuit using the static memory is unnecessary. In this embodiment, the input / output data 26 and 27, the delay amount control data 20, and the counter 1
Count data 23 output from 0 is displayed in parallel (1 to
k, 1-n, 1-m), but of course they may be serial ones.

[0016]

As is apparent from the above description, according to the present invention, the phase of input data can be flexibly adjusted by controlling the delay amount from the outside without changing the circuit configuration. Further, even if the range of the phase adjustment amount, that is, the delay amount is large, there is an effect that the circuit configuration can be made small.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a phase adjustment circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart showing an operation example when the delay amount is “3” in the phase adjustment circuit of this embodiment.

[Explanation of symbols]

 10 counter 11 comparator 12 latch circuit 13 FIFO memory 20 delay amount control data 21 delay amount control data latch signal 22 clock 23 counter output signal 24 latch circuit output data 25 comparison result signal 26 input data 27 output data

Claims (2)

[Claims] 1. A synchronous self-load counter that counts the number of clocks of an input clock and an input delay amount data and count data of the counter are compared to generate a comparison result signal when the two match. A comparator that resets the count data of the counter with a comparison result signal;
A phase adjustment circuit comprising: a FIFO memory that receives input data at the input timing of one comparison result signal and outputs the input data at the input timing of the next comparison result signal. 2. A latch circuit for temporarily holding the delay amount data and guiding the held delay amount data to the comparator at a predetermined timing.
The described phase adjustment circuit.