JPS63199538A - Synchronizing device for digital data signal - Google Patents

Abstract

PURPOSE:To make the phase coincident with a reference phase in following a wide variety of phase change by reading a digital data signal from a memory so that the phase is made coincident with a reference phase when a detected frame synchronizing signal is within a 2nd window having a larger width than that of a 1st window. CONSTITUTION:A digital voice signal of parallel 4-bit from a serial/parallel conversion circuit 202 is fed to a memory 203 and stored, the 4-bit parallel digital voice signal is fed to a parallel/serial conversion circuit 205 and converted into an original serial digital voice signal. The memory 203 is loaded once every supply of two preamble signals X or Z and the address of the address signal is restored to the initial address. Thus, so long as the preamble signal X of the input digital voice signal from the pin 1 is in the 2nd digital window having the window width in 64-bit corresponding to two frames of the digital voice signal decided by the capacity of the memory 203, the frame signal is read all at the reference phase.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a synchronization device for digital data signals.

[Summary of the invention]

The present invention provides synchronization of digital data signals that includes a memory, writes digital data signals in frame units to the memory, and reads out the digital data signals stored in the memory from the memory so that they are aligned with a reference phase for each frame. At the time of start setting, the device detects a frame synchronization signal of a digital data signal, and when the frame synchronization signal is within a first window having a predetermined window width, detects a digital data signal whose phase matches the reference phase. During normal operation, a frame synchronization signal of the digital data signal is detected, and the frame synchronization signal is within a second window having a predetermined window width larger than the window width of the first window. By reading the digital data signal from memory so that its phase matches the reference phase, when setting the start, the digital data signal is read out so that the phase of the digital data signal matches the reference phase. The phase can be automatically optimized, and during normal operation, the phase of the digital data signal can be automatically adjusted so that the phase of the digital data signal follows the wide range of phase changes and matches the reference phase. It has been made possible to do so.

[Conventional technology]

nothing special.

[Problem that the invention seeks to solve]

When there are multiple series of digital data signals in frame units, if you want to combine the digital data signals into one, it is necessary to synchronize the multiple series of digital data signals so that the phase of each frame matches the reference phase. There is.

In view of the above, the present invention is capable of automatically optimizing the phase of the digital data signal so that it matches the reference phase when setting the start, and at the same time, during normal operation, the phase of the digital data signal can be optimized so that the phase of the digital data signal matches the reference phase. The purpose of the present invention is to propose a digital data signal synchronization device that can automatically adjust the phase of a digital data signal so that the phase follows a wide range of phase changes and matches the reference phase.

[Means for solving problems]

The present invention includes a memory (203), writes a frame-by-frame digital data signal to the memory (203), and writes the digital data signal stored in the memory (203) to the memory (203) so that the digital data signal is aligned with the reference phase for each frame. 203)
In a digital data signal synchronization device configured to read data from a digital data signal, a frame synchronization signal of the digital data signal is detected during start setting, and when the frame synchronization signal is within a first window having a predetermined window width, the digital data signal is read from the digital data signal. The signal is read out from the memory (203) so that its phase matches the reference phase, and during normal operation,
A frame synchronization signal of a digital data signal is detected, and when the frame synchronization signal is within a second window having a predetermined window width larger than the window width of the first window, the digital data signal is detected, and when the frame synchronization signal is within a second window whose phase is the reference. It is read out from the memory (203) so that it matches the phase.

[Effect]

According to the present invention described above, at the time of start setting, the frame synchronization signal of the digital data signal is detected, and when the frame synchronization signal is within the first window having a predetermined window width, the digital data signal is Read from the memo IJ (203) so that it matches the reference phase,
During normal operation, a frame synchronization signal of a digital data signal is detected, and when the frame synchronization signal is within a second window having a predetermined window width larger than the window width of the first window, the digital data signal is detected. , read out from the memory (203) so that its phase matches the reference phase.

〔Example〕

An embodiment of the present invention will be described in detail below with reference to FIG. FIG. 1 is an example of a frame synchronization device for digital audio signals to which the present invention is applied. This frame synchronizer is composed of an l-chip IC (400) and an external circuit connected to it, which includes a signal processing section (200) equipped with a memory (203), and a signal processing section (200) equipped with a memory (203).
) and a read control section (300). In addition, IC (400)
is equipped with pins (1) to (24).

First, the write control section (100) will be explained. Bin (1) contains the bi-phase code Vriba AES/
Input digital audio signal in EBU format (its data rate is 128 fs = 6.144 MHz, where fs is the sampling frequency and is 48 kHz).
is supplied.

The format of this input digital audio signal is shown in FIG. An l frame (62 bits) digital audio signal is composed of two subframes (32 bits).

The first subframe consists of a frame synchronization signal (which also serves as a subframe synchronization signal) (sample preamble signal) and status bit signals V, U, C1P
The 0th order subframe consists of a subframe synchronization signal (sample preamble signal) Y, an auxiliary digital data signal, and a channel 2 (CH
2) (left channel) consists of a digital audio data signal and a status bit signal V, USCSP.

Furthermore, once every 192 frames, the preamble signal X is replaced with the preamble signal 2 (frame synchronization signal that also serves as a subframe synchronization signal). This is because the above-mentioned status bit signal ■ and the user's bit signal U of the USCSP constitute a unit of user's data for 192 frames, so the preamble signal Z is used to synchronize the user's data of that unit. It becomes a signal.

These pull preamplifier signals X, Y, and Z are the fourth
The waveforms are shown in Figures B, C, and A (the left and right waveforms are essentially the same, only 180 degrees out of phase), each of which is partially derived from the biphase rule. The waveform is out of place. In other words, the level of a bi-phase digital signal always inverts at the boundary between slots.
And when it is “1”, the level is reversed at the center of the slot (
However, the levels of the preamble signals Z, X, and Y shown in FIGS. 4A to 4C are not inverted at the boundary between slots 1 and 2.

Now, the input digital audio signal from pin (1) is supplied to a differentiating circuit (101) and differentiated, and the differentiated output is sent to an external preamble detection circuit (synchronization detection circuit) (102) through pin (2). A preamble detection pulse having a frequency of 2 fs is supplied to an external voltage controlled variable oscillator (103).

The frequency from the variable oscillator (103) is 256 fs or 3
An oscillation signal of 84 fs, that is, a write clock pulse (W
CK) with a dividing ratio of 1/2 or 1/2 via pin (7).
The signal is supplied to a frequency divider (counter) (106) of 3 and is frequency-divided (counted down). This frequency divider (106) is supplied with a write pulse selection signal (WCK) from pin (8).
5EL) is supplied, and the frequency division ratio (
1/2.1/3) are selected.

The clock pulse with a frequency of 128 fs from the counter (106) is passed through a frequency divider (counter) with a frequency division ratio of 1/64 (
105). A clock pulse with a frequency of 2 fs obtained from the frequency divider (105) is supplied to the variable oscillator (103) via pin (4).

The variable oscillator (103) has a built-in phase comparator, which detects the detection pulse with a frequency of 2 fs from the preamble detection circuit (102) and the frequency of 2 fs from the frequency divider (105). Compare the phase with the clock pulse,
Thereby, this oscillator (103) has a frequency of 256 fs or 384 fs, which is phase-locked to the input digital audio signal.
Outputs the f5 oscillation signal.

(104) is a write data existence detection circuit, and pin (3)
) and receives a detection pulse from a preamble detection circuit (102) and a signal indicating the presence or absence of write data from an input terminal (104a). And a variable oscillator (
103) is controlled by a write data presence detection circuit (104), which latches the detection pulse from the preamble detection circuit (102) and performs the above-mentioned phase comparison only when there is write data, and when there is no write data. is designed to hold the previous phase comparison result.

A detection output from the write data presence detection circuit (104) is supplied to an external display light emitting diode D1 through a pin (9).

(108) is a preamble decoder (preamble extraction circuit) which receives the input digital audio signal from pin (1). (107) is a wind pulse generation circuit, and the frequency divider (
A clock pulse having a frequency of 2 fs is received from a clock pulse generator (105), a wind pulse is generated based on the clock pulse, and this wind pulse is supplied to a preamble decoder (108) to avoid erroneous detection of a preamble signal. I have to. .

(110) is a write address generation circuit.

A clock pulse with a frequency of 128 fs from the frequency divider (1,06) is supplied to the frequency divider (109) with a frequency division ratio of 1/2 and is divided into 1/2, and the frequency obtained from this is is 5
A 4fs clock pulse is used by the write address generation circuit (
110). Preamble decoder (108
), the preamble signals x, y, z obtained from pins (10
), (11), and (12), and the preamble signals X, .

In addition, pin (17) is a test pin, pin (18) is +
The 5V power supply voltage input terminal, pin (6), is the ground terminal.

Next, the read control section (300) will be explained. A read clock pulse RCK with a frequency of 256 fs or 384 fs from a pin (20) is supplied to a frequency divider (counter) (302) with a frequency division ratio of 1/2 or 1/3 and is divided (counted down). . This ψ frequency divider (302) receives a read pulse selection signal (RCK) from the pin (19).
5EL) is supplied and the read clock pulse R
A frequency division ratio (1/2.1/3) is selected depending on the CK frequency of 256 fs or 384 fs. This frequency divider (302
) has a reference preamble signal RE from pin (21).
FX is supplied.

(307) is a detection circuit for the preamble signal Y, to which the preamble signal Y from the preamble decoder (10B) of the write control circuit (100) is supplied, and from this detection circuit (307) the preamble signal Y is supplied. A Y detection pulse is obtained.

(30B) is a discrimination circuit which receives the detection pulse of the reference preamble signal REF X from the pin (21) and the preamble signal Y from the detection circuit (307).
), a discrimination pulse is generated when the reference preamble signal REF X closest to the preamble signal Y of the input digital audio signal is detected.

(304) is a read address generation circuit.

A clock pulse with a frequency of 128 fs from the frequency divider (302) is supplied to the frequency divider (303) with a frequency division ratio of 1/2! /2, and the resulting frequency is 54
The fs clock pulse is used by the read address generation circuit (3
04). This read address generation circuit (
304) is supplied with advance select signals ADV-1 and ADV-0 from pins (15) and (14), as well as a discrimination pulse from a discrimination circuit (308) as a load pulse.

These 2-bit advance select signals ADV-1, A
According to DV-0, the readout timing of the digital audio signal read out from the memory (203) of the signal processing unit (200), which will be described later, is changed to four minute phase states, and the readout digital audio signal is The relative phase of the preamble signal to the signal can be changed into four states.

(301) is a reference preamble signal REFX presence detection circuit, which is supplied with the reference preamble signal REFX from pin (21). The presence detection signal of the reference preamble REF
) is supplied to an external display light emitting diode D2.

(306) is a reset pulse generation circuit, which includes a reset pulse R generated when power is turned on from pin (13).
3T, reference preamble signal X presence detection circuit (301
The presence detection signal of the reference preamble REF 304) and write control unit (100)
Write address generation circuit (110) t: Supplied as a load pulse.

In addition, in FIG. 5, the read clock pulse RCK is 25.
6 fs and 384 fs, the reference preamble signal REFX (A, F in the same figure), the frequency is 256 fs/
A clock pulse of 384 fs (B, G in the same figure), a load pulse (C5H in the same figure), a clock pulse with a frequency of 128 fs (I in the same figure), and a clock pulse of 64 fs (
The waveforms of E and J) in the same figure are shown.

(305) is a preamble generation circuit, to which a read address signal from the read address generation circuit (304) is supplied. This preamble generation circuit (305
), the frequencies in Figure 6 A and B are 64 fs and 12 fs, respectively.
Figure 6 C, D, E synchronized with 8fs clock pulse
The preamble signal RZX (return zero) shown in
RZ Y and RZ Z, and the nonreturn-to-zero preamble signal NRZ X shown in FIG. 6 F, G, and H.
NRZ Y, NRZ Z occur.

Next, the signal processing section (200) will be explained.

(201) is an AES/EBU decoder, to which a bi-phase digital audio signal in AES/EBtJ format is supplied from pin (1).

A digital audio signal of RZ code is obtained from this decoder (201), and this is sent to the serial-parallel conversion circuit (202).
The signal is supplied to the audio signal and converted into a parallel 4-bit digital audio signal. (2Q 3) is memory, 128 (=32X4
) bits, which is exactly the capacity to store two frames of digital audio signals.

(204) is a memory control circuit for this memory (203), which includes a clock pulse with a frequency of 64 fs from the frequency divider (109) of the write control circuit (lOO), and a clock pulse with a frequency of 64 fs from the read address generation circuit (110). Read address signal and write address generation circuit (30
4) is supplied with a write address signal. The frequency from this memory control circuit (204) is 64f.
s clock pulses and write and read address signals are provided to the memory (203).

The parallel 4-bit digital audio signal from the serial-to-parallel conversion circuit (202) is supplied to the memory (203), where it is written and stored, and the 4-bit parallel digital audio signal read from this is subjected to parallel-to-serial conversion. The signal is supplied to a circuit (205) and converted into the original serial digital audio signal.

(206) is an RZ preamble insertion circuit, (207) is an NRZ preamble insertion circuit, and these preamble insertion circuits (206) and (207) receive the serial digital audio signal from the parallel-to-serial conversion circuit (205). is supplied. Then, preamble signals RZX, Y, Z (C, 1 in FIG. 6), L from the preamble generation circuit (305)
! ：Nokani is supplied to the preamplifier insertion circuit (206) and inserted into the serial digital audio signal, and the preamble signal is changed.
05) Preamble signal NRZ X, Y, Z
(FIG. 6F, GSH) is supplied to the NRZ pull insertion circuit (205) and added to the serial digital audio signal to replace the preamble signal.

The output of the RZ preamble insertion circuit (206) is AES,
/EBU encoder (20B), where it is encoded and a digital audio signal in AES/EBU format with a data rate of 128 fs is output to pin (24). Further, the output of the RZ preamble insertion circuit (206) is supplied to an inverter (209) and phase inverted, thereby outputting an RZ code digital audio signal to the bin (22). Also, NRZ preamplifier insertion circuit (
A digital audio signal of NRZ code with a frequency of 128 fs from the bin (207) is output to the bin (23).

The writing and reading operations for the memory (203) of the digital audio signal frame synchronization device shown in FIG. 1 will be explained with reference to FIG. 2 below. Figures 2A-D show various phases of the frame signal of the input digital audio signal being written into the memory (203).

FIG. 2E shows an output digital audio signal read out from the memory (203) and with the preamble signal assigned to it changed so that its phase matches the reference phase.

The write address signal generation circuit (110) is a memory
As mentioned above, (203) has a capacity that can store two frames of the input digital audio signal, so it is loaded once every two preamble signals X or 2 are supplied to it. ζ, the address of the address signal is returned to the initial address, and each time the serial-parallel conversion circuit (
202) is written into the memory (203) for two frames from the preamble signal X or Z.

Further, the read address signal generation circuit (304) is loaded once every two reference preamble signals REF X closest to the preamble signal Y of the input digital audio signal from pin (1) are supplied. The address of the address signal is returned to the first address, and each time the parallel digital audio signal is read out for two frames from the preamble signal X or Z, and the read parallel digital audio signal The timing of the position of the preamble signal X or Z is made to match the timing of the reference preamble signal REFX.

Therefore, unless the read address generation circuit (304) is reset by a reset signal from the reset circuit (306), the preamble signal X of the input digital audio signal from pin (1) will be
(203) with the preamble signal X, as long as the preamble signal All frame signals are read out at the reference phase as shown in FIG. 2E.

Note that the phase of the center of the second window is l frames earlier than the phase of the reference preamble signal REF X in FIG. 2E.

The reset pulse generation circuit (306) generates a signal when the power is turned on, when the input digital audio signal is no longer supplied to pin (1) (that is, when the input preamble signal X is no longer detected), and when the reference preamble signal REF Generates a reset pulse when no longer detected. When this reset pulse is generated, it is activated by the write address generation circuit (107) and the read address generation circuit (107).
304) and are loaded together to cause the address of the address signal to return to the original address.

Therefore, when a reset pulse is generated from the reset pulse generation circuit (306), as shown in FIG. 3 corresponding to the mu minute
As long as it is within the first window having a window width of 2 bits, the frame signals of FIG. 2B-D with the preamble signal X are all read out at the reference phase as shown in FIG. 2E. Become. The phase of the center of this first window is the same as the phase of the center of the second window.

〔Effect of the invention〕

According to the present invention described above, during start setting, the phase of the digital data signal can be automatically optimized so that the phase of the digital data signal matches the reference phase, and during normal operation, the phase of the digital data signal can be automatically optimized so that the phase of the digital data signal matches the reference phase. It is possible to obtain a digital data signal synchronization device that can automatically adjust the phase of a digital data signal so that the phase follows a wide range of phase changes and matches the reference phase.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a frame synchronization device for digital audio signals to which the present invention is applied, FIG. 2 is a conceptual diagram of its operation, FIG. 3 is a diagram showing the formant of digital audio signals, and FIG. 4 5 is a timing chart showing the preamble signal, FIG. 5 is a timing chart showing generation of a read clock pulse, and FIG. 6 is a timing chart showing the preamble signal. (100) is a write control unit, (200) is a signal processing unit, (300) is a read control unit, (203) is a memory,
(204) is a memory control circuit.

Claims (1)

[Scope of Claims] A device comprising a memory, writing a frame-by-frame digital data signal into the memory, and reading out the digital data signal stored in the memory from the memory so as to be aligned with a reference phase for each frame. In the digital data signal synchronization device, when setting the start, a frame synchronization signal of the digital data signal is detected, and when the frame synchronization signal is within a first window having a predetermined window width, the digital data signal is synchronized with the digital data signal. The signal is read from the memory so that its phase matches the reference phase, and during normal operation, a frame synchronization signal of the digital data signal is detected, and the frame synchronization signal is larger than the window width of the first window. When the digital data signal is within a second window having a large predetermined window width, the digital data signal is read out from the memory so that its phase matches the reference phase. synchronizer.