JPH0396026A - Synchronizing word detection system - Google Patents

Abstract

PURPOSE:To detect a synchronization word by both the hardware and the software by storing a reception data even in the case of a synchronization word to an input buffer register similarly in the case of a data word and recognizing the data with a central processing unit according to a synchronization word reception status. CONSTITUTION:Even when a reception data is a synchronization word, the reception data is set to an IBR(input buffer register) 18 so as to allow a central processing unit 19 to read the data similary in the case of a data word. Moreover, a synchronizing word detection circuit 15 decides whether the data set in the IBR 18 is a data word or a synchronization word and outputs the decision result as a synchronization word reception status output from a reception status generating circuit 21. Thus, the hardware decision result of the data set to the IBR 18 is recognized by the CPU 19.

Description

[Detailed Description of the Invention] [Summary] Regarding a method for detecting a synchronization word from data including a synchronization word and a data word, we have developed a circuit structure that enables detection of a synchronization word using both hardware and software. In order to improve the reliability of synchronization word detection, one frame of received data is composed of one synchronization word and n data words. A circuit comprising a serial-to-parallel conversion circuit for processing, an input buffer register for storing the output of the series-to-parallel conversion circuit, and a central processing unit for controlling readout of data stored in the input buffer register, the circuit comprising: A received data change detection circuit that detects a change in received data, a sync word detection circuit that detects a sync word in the received data, and an AND of both outputs of the sync word detection circuit and the received data change detection circuit (12). If there is a product output, the clock is reset to the AND product output and synchronized with the received data, and if there is no output from the synchronization word detection circuit, it is not synchronized with the received data and the clock is output. A baud rate cross signal generation circuit that outputs a cross signal that remains synchronized with the synchronization word detection circuit, a fall detection circuit that detects the fall time of the output of the synchronization word detection circuit, and a fall detection circuit that counts the output of the baud rate crosstalk generation circuit. a bit counter that outputs a latch pulse that causes the input buffer register to latch the received data at a predetermined timing, and is reset by the output of the falling edge detection circuit; and both outputs of the synchronization word detection circuit and the bit counter. and a reception status generation circuit that outputs a synchronous word reception status from the synchronous word, and even if the received data is a synchronous word, it is stored in the impossator register in the same way as a data word, and the data is recognized by the central processing unit. is made possible by the synchronization word reception status.

[Industrial application field]

The present invention relates to a method for detecting a synchronization word from data including a synchronization word and a data word.

[Conventional technology]

FIG. 4 is a diagram showing a circuit structure of a conventional embodiment. In the figure, 31 is an oscillator, 32 is a received data change detection circuit, 3
3 is a baud rate clock generation circuit, 34 is an AND circuit,
35 is a synchronization word detection circuit, 36 is a bisoto counter, 3
7 is a serial-to-parallel conversion circuit, 38 is an input buffer register (hereinafter referred to as IBR), and 39 is a central processing unit (hereinafter referred to as CPU).

Note that FIGS. 5 and 6 are diagrams showing examples of time charts in conventional circuits. FIG. 5 is a synchronization time chart between a synchronization word and a data word, and FIG. This is a synchronization time chart.

First, synchronization between a synchronization word and a data word will be explained with reference to FIGS. 4 and 5. Received data (a) includes data word 1 of one synchronization word and n data words;
Data word 2: data composed of data word n. These received data (a) are always controlled by the baud rate crosslink (bl) and are sent to the serial-to-parallel converter circuit 37.
It has been received in

In the received data change detection circuit 32, this received data fa
Compare t with the output from the oscillator 3l to obtain the received data (a)
The data change detection result (C) is outputted and added to the AND circuit 34.

On the other hand, when the synchronization word detection circuit 35 detects a synchronization word from the manually inputted received data (al), a bit synchronization permission signal (d) of, for example, 16 bits is output to the AND circuit 34. AND circuit 3
In step 4, the output (C) and the output (d) are ANDed and a recent signal +114) is output to reset the baud rate cross signal generator 33, and the baud rate cross signal (b
l is output to the series-to-parallel conversion circuit 37.

Therefore, the output is synchronized with the porate clock (bl is received data!8) from the porate clock generation circuit 33. Note that the synchronization word detection circuit 35 resets the bit counter 36 by outputting a synchronization word detection result (f) that is delayed by a half cycle from the received data (a). For this purpose, the IBR latch pulse from the bisoto counter 36 (there is no phantom output, and therefore the series-to-parallel converter circuit 3
The synchronization word in the received data (al) output from the IBR 38 is not latched.

Next, synchronization in the case of synchronization word 1 and data word 2, for example, will be explained with reference to FIGS. 4 and 6.

The received data change detection circuit 32 compares the received data (al) with the output from the oscillator 3l to detect changes and outputs a data change detection result (C), but the received data (a) does not include a synchronization word. Therefore, the bit synchronization permission signal (dl) from the synchronization word detection circuit 35 is not output, and therefore the reset signal tel is not output from the AND circuit 34. Therefore, the baud rate clock generation circuit 33 is not reset, and therefore the baud rate The baud rate clock (bl) of the clock generation circuit 33 is not synchronized with the received data (al). In other words, it is not synchronized when receiving the data word.
) in order not to reset the bit counter 36 by I
BR latch pulse (O is output to IBR38, data word 1 from series-to-parallel conversion circuit 37 is output to IBR3
Lunch will be served at 8.

That is, as described above, when receiving the synchronization word, the received data (a) is not set in the IBR 38. In other words, if it is determined that it is a synchronization word, the IBR latch pulse is used to seset the received data (a) to the IBR38 (the function to suppress the occurrence of phantoms is performed only by hardware,
For this reason, for example, if the reading from the IBR 38 by the CPU 39 malfunctions, there is a possibility that the synchronization word will be erroneously detected, and therefore a method for increasing the reliability of synchronization word detection is required.

[Problem to be solved by the invention]

Therefore, the hardware identifies whether the received word is a data word or a synchronization word, sets only the data word in the IBR38, and sets the synchronization word in the IBR38.
, the software of the CPU 39 that reads the contents of the IBR 38 cannot detect the synchronization word.

An object of the present invention is to improve the reliability of synchronization word detection by providing a circuit structure that allows synchronization word detection to be performed using both hardware and software.

[Means to solve the problem]

In the present invention, one frame of received data is composed of l synchronization words and n data words, and a series-to-parallel conversion circuit 17 that converts the received data from serial data to parallel data using a clock; Conversion circuit 17
an input buffer register 18 that stores the output of
In a circuit including a central processing unit 19 that controls reading of data stored in the input buffer register 18, a received data change detection circuit 12 detects a change in the received data, and a synchronization word in the received data is detected. AND of the outputs of the synchronization word detection circuit 15 and the received data change detection circuit 12.
If there is a product output, it is reset to the AND product output and outputs the clock that is synchronized with the received data, and if there is no output from the synchronization word detection circuit 15, it does not synchronize with the received data. A baud rate clock generation circuit 13 that outputs the same clock as previously synchronized, a falling detection circuit 20 that detects the falling time of the output of the synchronization word detection circuit 15, and the output of the baud rate clock generation circuit 13. a synchronous word detection circuit; Reception status generation circuit 2 outputs the synchronization word reception status from both outputs of bit counter 15 and bit counter 16.
Even if the received data is a synchronous word, it is stored in the input buffer register 18 in the same way as a data word, and the data can be recognized by the central processing unit based on the synchronous word reception status. It is something to do.

[For production]

In the present invention, in the circuit configuration shown in FIG. 1, when receiving a synchronization word, similarly to when receiving a data word, the received data is transferred to the IBR by the IBR latch pattern from the bit counter 16.
A circuit structure is used to set the IBR18 to R18, and a reception status generating circuit 21 determines whether the data stolen to the IBR18 is a sync word or a data word, and generates a sync word status signal only when a sync word is received. The data is then sent to the central processing unit l9.

Therefore, the software of the central processing unit 19 can verify the sync word by checking the IBR1B using the sync word status signal, and further check the sync word detection between hardware and software using the sync word status signal. Since judgment verification is possible, high reliability of synchronization word detection is made possible by duplication of hardware and software.

〔Example〕

FIG. 1 is a diagram showing the circuit structure of the present invention. In the figure, ll
is an oscillator, 12 is a received data change detection circuit, 13 is a baud rate clock generation circuit, l4 is an AND circuit, 15 is a synchronization word detection circuit, 16 is a bit counter, 17 is a series-to-parallel conversion circuit, 18 is an IBR, and 19 is a CPU. and
The circuits up to this point have the same functions as those in FIGS. 4 to 6. Further, 20 and 21 are circuit parts of the present invention, 20 is a falling detection circuit, and 2l is a reception status generation circuit.

Note that Figures 2 and 3 are diagrams showing examples of time charts in conventional circuits. Figure 2 is a synchronization time chart between a synchronization word and a data word, and Figure 3 is a synchronization time chart between a data word and a data word. This is a synchronization time chart between

First, synchronization between a synchronization word and a data word will be explained with reference to FIGS. 1 and 2. As in the conventional example, the received data (a) is data composed of one synchronization word and n data words, data word 1, data word 2, . . . data word n. This received data (a
) is always received by the serial-to-parallel conversion circuit 17 under the control of the porate clock (C). The received data change detection circuit 12 detects this received data (a
Compare l with the output of oscillator 1l and find out that the received data (a) is “
A change is detected between the l゛ level and the "0' level, and the obtained data change detection result +d) is added to the AND circuit l4. On the other hand, the synchronization word detection circuit 15 detects synchronization from the manually generated received data (a). If a word is detected, a bit synchronization enable signal (Q
) is output to the AND circuit l4.

Therefore, in the AND circuit l4, the output (dl) and the output (I
l! ), a reset signal (f) is output and the baud rate clock generation circuit 13 is reset, and the baud rate clock generation circuit 13 outputs a baud rate clock (C) synchronized with the received data (a). . Therefore, the received data (al and baud rate clock generation circuit 13
baud rate clock (C) can be synchronized.

In addition, the synchronous word detection circuit 15 outputs the synchronous word detection result (river) delayed by half a cycle from the received data (a). This synchronous word detection result (g) is manually inputted to the falling edge detection circuit 20, A falling detection result (h) is output at the falling timing of the detection result (g).The IBR latch pulse (1) output from the bisoto counter 16 is output at the falling timing of the received data (a). Since the fall detection result (hl) is reset at the timing after the IBR latch pulse (1) is output, the synchronization word is IBR1B
Becomes latched.

Note that when outputting IBR latch pulse 41, the reception status generation circuit 2l latches the synchronization word detection result (g) and outputs the synchronization word reception status mountain that changes from "Low" to "old gh") to the CPU 19. .

The synchronization between, for example, the synchronization word I and the data word 2 will now be explained with reference to FIGS. 1 and 3. FIG.

The received data change detection circuit 12 detects this received data (a
) and the output of the oscillator 11 to detect a change in the received data (a), and output the data change detection result (d) and add it to the AND circuit l4. On the other hand, the synchronization word detection circuit 15 does not output the bisoto synchronization permission signal (e) because the manually generated received data fa) does not include a synchronization word and is only synchronization data. For this reason, in the AND circuit l4,
The reset signal (f) obtained by ANDing the output (dl and the output (e)) is not output. Therefore, the baud rate clock generation circuit 13 is not reset, and the received data (a
) and the baud rate clock (C) of the baud rate clock generation circuit 13 are not synchronized. In other words, there is no synchronization when receiving data words. Note that the synchronous word detection result (phantom) from the synchronous word detection circuit 15 is input to the falling edge detection circuit 20 together with the output from the oscillator 11 to reset the falling edge detection circuit 20. Since there is no synchronization word detection result (g), the falling detection result from the falling detection circuit 20 (
There is no output of hl, so the bint counter 16 is not set and outputs an IBR latch pulse (1). Therefore, from the bit counter 16, the IBR laser pulse (1)
is input to the BR18, and the data word from the serial-to-parallel conversion circuit 17 is latched into the II3R18 in the same way as in the case of the synchronization word and data word as shown in FIG. Note that the IBR latch pulse (1) is output when the synchronization word is not detected by the synchronization word detection circuit I5, and in this case, the synchronization word reception status (bl is "old") output from the reception status generation circuit 2l. gh'
to "Low" and stops its output.

As described above, in the present invention, even if the received data (a) is a synchronous word, the received data (al) is sent to the IBR 18 so that the central processing unit 19 can read it in the same way as a data word.
Further, the synchronization word detection circuit 15 determines whether the data set in IBR1B is a data word or a synchronization word, and the result is output as a determination result from the reception status generation circuit 21 as a synchronization word reception status output. , it is possible for the CPU 19 to recognize the hardware determination results of the data stored in the IBR1B. By doing this, the software of the CPU 19 can detect the synchronization word by reading IBRlB, and compare the synchronization word reception status, which is the result of the detection of the hardware, with the result of the detection of the synchronization word by the CPU software. Since the synchronization word detection can be performed redundantly, the reliability of the synchronization word detection can be increased.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, since synchronization word detection can be performed using both hardware and software, it is possible to contribute to high reliability of synchronization word detection.

[Brief explanation of drawings]

Figure 1 is a diagram showing the circuit configuration of the present invention. Figure 2 is a diagram showing an example of a time chart in the circuit of the present invention. Figure 3 is a diagram showing another example of a time chart in the circuit of the present invention. , Fig. 4 is a diagram showing a circuit configuration of a conventional example, Fig. 5 is a diagram showing an example of a time chart in the conventional circuit, and Fig. 6 is a diagram showing another example of a time chart in the conventional circuit. , is a diagram showing , . In the figure, 12 is a received data change detection circuit, 13 is a baud rate clock generation circuit, 15 is a synchronization word detection circuit, 16 is a bit counter, 17 is a serial-to-parallel conversion circuit, 18 is an input buffer register, l9 is a central processing unit, (CPU) 20 is a falling detection circuit, and 21 is a reception status generation circuit. (IBR) O 4 An FJF 4 A group f to z Hei Guim chart's death sentence T figure 1! H'n synchronization 7-1-" An example of 7 im thousand yats of unexploded gR recessed tsuba parable.
el

Claims (1)

[Claims] a serial-to-parallel conversion circuit (17) that configures one frame of received data from one synchronization word and n data words, and converts the received data from serial data to parallel data using a clock; and the serial-to-parallel conversion circuit. an input buffer register (18) that stores the output of (17);
The circuit includes a central processing unit (19) that controls reading of data stored in the input buffer register (18), and includes a received data change detection circuit (12) that detects a change in the received data; If there is an AND product output of the synchronization word detection circuit (15) that detects the synchronization word in the AN, and the output of both the synchronization word detection circuit (15) and the received data change detection circuit (12), the AN
The clock is reset to the D product output and synchronized with the received data, and the synchronization word detection circuit (1
If there is no output of 5), the baud rate clock generation circuit (13) outputs the previously synchronized clock without synchronizing with the received data, and the output of the synchronization word detection circuit (15). A fall detection circuit (20) that detects the fall time and the output of the baud rate clock generation circuit (13) are counted and a latch pulse is outputted at a predetermined timing to cause the input buffer register (18) to latch the received data. and a bit counter (16) that operates to be reset by the output of the falling edge detection circuit (20), and a synchronization word reception status from both outputs of the synchronization word detection circuit (15) and the bit counter (16). Even if the received data is a synchronous word, it is stored in the input buffer register (18) in the same way as a data word, and the data is recognized by the central processing unit. A synchronization word detection method characterized by being made possible by the synchronization word reception status.